Issued Patents All Time
Showing 1–25 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381552 | Power on control circuits and methods of operating the same | Po-Zeng Kang, Yung-Chow Peng | 2025-08-05 |
| 12349469 | Stack-gate circuit | Yu-Tao Yang, Yung-Chow Peng | 2025-07-01 |
| 12339174 | Temperature monitoring device and method | Po-Zeng Kang, Yung-Chow Peng | 2025-06-24 |
| 12299370 | Systems and methods for providing a dynamic high voltage circuit design workflow | Shenggao Li, Szu-Chun Tsao | 2025-05-13 |
| 12272640 | Semiconductor device with source resistor | Po-Zeng Kang, Yung-Chow Peng | 2025-04-08 |
| 12254257 | High voltage guard ring semiconductor device and method of forming same | Ming-Cheng Syu, Po-Zeng Kang, Yung-Hsu Chuang, Shu-Chin Tai, Yung-Chow Peng | 2025-03-18 |
| 12249601 | Integrated circuit device, method, layout, and system | Po-Zeng Kang, Yung-Chow Peng | 2025-03-11 |
| 12199086 | Stack-gate circuit | Yu-Tao Yang, Yung-Chow Peng | 2025-01-14 |
| 12169675 | Automatic generation of layouts for analog integrated circuits | Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang | 2024-12-17 |
| 12147752 | Pre-characterization mixed-signal design, placement, and routing using machine learning | Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang | 2024-11-19 |
| 12118287 | Automatic generation of sub-cells for an analog integrated circuit | Chih-Chiang Chang, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina | 2024-10-15 |
| 12106031 | Transition cells for advanced technology processes | Yung-Hsu Chuang, Yung-Chow Peng, Yu-Tao Yang, Yun-Ru Chen | 2024-10-01 |
| 12087814 | Semiconductor devices and methods of manufacturing thereof | Chia-Chung Chen, Yung-Chow Peng, Ya Yun Liu | 2024-09-10 |
| 11914940 | System for designing a semiconductor device, device made, and method of using the system | Jaw-Juinn Horng, Yung-Chow Peng | 2024-02-27 |
| 11898916 | Device for temperature monitoring of a semiconductor device | Po-Zeng Kang, Yung-Chow Peng | 2024-02-13 |
| 11847399 | Integrated circuit with asymmetric mirrored layout analog cells | Yu-Tao Yang, Yung-Chow Peng | 2023-12-19 |
| 11816414 | Automatic generation of sub-cells for an analog integrated circuit | Chih-Chiang Chang, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina | 2023-11-14 |
| 11763060 | Automatic generation of layouts for analog integrated circuits | Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang | 2023-09-19 |
| 11711076 | Power on control circuits and methods of operating the same | Po-Zeng Kang, Yung-Chow Peng | 2023-07-25 |
| 11704470 | Pre-characterization mixed-signal design, placement, and routing using machine learning | Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang | 2023-07-18 |
| 11670586 | Semiconductor device with source resistor and manufacturing method thereof | Po-Zeng Kang, Yung-Chow Peng | 2023-06-06 |
| 11429775 | Automatic generation of sub-cells for an analog integrated circuit | Chih-Chiang Chang, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina | 2022-08-30 |
| 11309306 | Stack-gate circuit | Yu-Tao Yang, Yung-Chow Peng | 2022-04-19 |
| 11270057 | Semiconductor device including regions for reducing density gradient effect and method of forming the same | Yu-Tao Yang, Yung-Hsu Chuang, Yung-Chow Peng | 2022-03-08 |
| 11238207 | Method and system for fabricating integrated circuit with aid of programmable circuit synthesis | Yung-Hsu Chuang, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yun-Ru Chen | 2022-02-01 |