Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381552 | Power on control circuits and methods of operating the same | Wen-Shen Chou, Yung-Chow Peng | 2025-08-05 |
| 12339174 | Temperature monitoring device and method | Wen-Shen Chou, Yung-Chow Peng | 2025-06-24 |
| 12272640 | Semiconductor device with source resistor | Wen-Shen Chou, Yung-Chow Peng | 2025-04-08 |
| 12254257 | High voltage guard ring semiconductor device and method of forming same | Ming-Cheng Syu, Yung-Hsu Chuang, Shu-Chin Tai, Wen-Shen Chou, Yung-Chow Peng | 2025-03-18 |
| 12249601 | Integrated circuit device, method, layout, and system | Wen-Shen Chou, Yung-Chow Peng | 2025-03-11 |
| 11898916 | Device for temperature monitoring of a semiconductor device | Wen-Shen Chou, Yung-Chow Peng | 2024-02-13 |
| 11711076 | Power on control circuits and methods of operating the same | Wen-Shen Chou, Yung-Chow Peng | 2023-07-25 |
| 11670586 | Semiconductor device with source resistor and manufacturing method thereof | Wen-Shen Chou, Yung-Chow Peng | 2023-06-06 |
| 11215513 | Device and method for temperature monitoring of a semiconductor device | Wen-Shen Chou, Yung-Chow Peng | 2022-01-04 |
| 11217526 | Semiconductor device with source resistor and manufacturing method thereof | Wen-Shen Chou, Yung-Chow Peng | 2022-01-04 |
| 10872189 | Uni-gate cell design | Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang | 2020-12-22 |
| 10514417 | IC degradation management circuit, system and method | Chih-Hsien Chang, Wen-Shen Chou, Yung-Chow Peng | 2019-12-24 |
| 10401407 | Output resistance testing integrated circuit | Wen-Shen Chou, Yung-Chow Peng | 2019-09-03 |
| 10274536 | Time to current converter | Yung-Chow Peng, Wen-Shen Chou, Yu-Tao Yang | 2019-04-30 |
| 10222412 | IC degradation management circuit, system and method | Chih-Hsien Chang, Wen-Shen Chou, Yung-Chow Peng | 2019-03-05 |
| 10161976 | Output resistance testing method | Wen-Shen Chou, Yung-Chow Peng | 2018-12-25 |
| 10018660 | Output resistance testing structure | Wen-Shen Chou, Yung-Chow Peng | 2018-07-10 |
| 9659919 | Nearly buffer zone free layout methodology | Yung-Chow Peng, Jaw-Juinn Horng, Szu-Lin Liu | 2017-05-23 |
| 9429607 | Low gds measurement methodology for MOS | Yung-Chow Peng | 2016-08-30 |
| 9343552 | FinFET with embedded MOS varactor and method of making same | Wan-Te Chen, Chung-Hui Chen, Jaw-Juinn Horng | 2016-05-17 |
| 9287252 | Semiconductor mismatch reduction | Chung-Hui Chen, Ruey-Bin Sheen, Yung-Chow Peng, Chung-Peng Hsieh | 2016-03-15 |
| 9064725 | FinFET with embedded MOS varactor and method of making same | Wan-Te Chen, Chung-Hui Chen, Jaw-Juinn Horng | 2015-06-23 |
| 8916955 | Nearly buffer zone free layout methodology | Yung-Chow Peng, Jaw-Juinn Horng, Szu-Lin Liu | 2014-12-23 |
| 8856707 | Semiconductor device feature density gradient verification | Young-Chow Peng, Chung-Hui Chen, Chien-Hung Chen | 2014-10-07 |
| 8549453 | Semiconductor device feature density gradient verification | Young-Chow Peng, Chung-Hui Chen, Chien-Hung Chen | 2013-10-01 |