Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12299370 | Systems and methods for providing a dynamic high voltage circuit design workflow | Shenggao Li, Wen-Shen Chou | 2025-05-13 |
| 12265411 | Low-dropout (LDO) voltage regulator including amplifier and power down control unit (PDCTRL) | Yi-Wen Chen, Jaw-Juinn Horng | 2025-04-01 |
| 12242292 | Circuit for outputting a stepdown voltage and method for stepping down a voltage | Bindu Madhavi Kasina, Jaw-Juinn Horng | 2025-03-04 |
| 12183731 | Dummy device for core device to operate in a safe operating area and method for manufacturing the same | Jaw-Juinn Horng | 2024-12-31 |
| 12147255 | LDO/band gap reference circuit | Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen | 2024-11-19 |
| 12106809 | System and method for reliable sensing of memory cells | Jaw-Juinn Horng | 2024-10-01 |
| 12093065 | Digital low-dropout voltage regulator | Po-Yu Lai, Jaw-Juinn Horng | 2024-09-17 |
| 12087389 | Device and method for reading data in memory | Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng | 2024-09-10 |
| 12057177 | Bias control for memory cells with multiple gate electrodes | Jaw-Juinn Horng | 2024-08-06 |
| 11906997 | Low-dropout (LDO) voltage regulator including amplifier and decoupling capacitor | Yi-Wen Chen, Jaw-Juinn Horng | 2024-02-20 |
| 11853880 | SRAM architecture for convolutional neural network application | Jaw-Juinn Horng | 2023-12-26 |
| 11763891 | System and method for reliable sensing of memory cells | Jaw-Juinn Horng | 2023-09-19 |
| 11733724 | Digital low-dropout voltage regulator | Po-Yu Lai, Jaw-Juinn Horng | 2023-08-22 |
| 11726510 | Circuit and method for stepping down a voltage | Bindu Madhavi Kasina, Jaw-Juinn Horng | 2023-08-15 |
| 11669115 | LDO/band gap reference circuit | Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen | 2023-06-06 |
| 11430491 | Device and method for reading data in memory | Jaw-Juinn Horng, Chin-Ho Chang, Yung-Chow Peng | 2022-08-30 |
| 11257550 | Bias control for memory cells with multiple gate electrodes | Jaw-Juinn Horng | 2022-02-22 |
| 10958259 | Pulse width modulation output stage with dead time control | Yang-Jing Huang, Ya-Mien Hsu | 2021-03-23 |
| 10404227 | Quaternary/ternary modulation selecting circuit and associated method | Deng-Yao Shih | 2019-09-03 |
| 10050432 | Apparatus with load dump protection | — | 2018-08-14 |
| 9977459 | Clock generating circuit and associated method | Chin-Tung Chan, Deng-Yao Shih | 2018-05-22 |
| 9748911 | Variable gain amplifying circuit | Deng-Yao Shih | 2017-08-29 |
| 9705315 | Protection circuit for preventing an over-current from an output stage | — | 2017-07-11 |
| 9300281 | Triangular wave generating circuit to provide clock synchronization | — | 2016-03-29 |