Issued Patents All Time
Showing 1–25 of 194 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412605 | Bit line pre-charge circuit and method | Che-Ju Yeh, Yu-Hao Hsu, Hau-Tai Shieh | 2025-09-09 |
| 12400723 | Latch type sense amplifier for testing | Hua-Hsin Yu, Hau-Tai Shieh, Hung-Jen Liao | 2025-08-26 |
| 12400708 | Memory device and method for reducing active power consumption thereof using address control | Chien-Yuan Chen, Hau-Tai Shieh | 2025-08-26 |
| 12380945 | Memory device with word line pulse recovery | Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang | 2025-08-05 |
| 12354647 | Memory device sense amplifier control | Chien-Yuan Chen, Hau-Tai Shieh | 2025-07-08 |
| 12347483 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Hau-Tai Shieh, Hung-Jen Liao | 2025-07-01 |
| 12340871 | Memory circuits with dynamically adjustable pulse widths and methods for operating the same | Ming-Hung Chang, Chia-Cheng Chen, Ching-Wei Wu | 2025-06-24 |
| 12322438 | Latch circuit formed by modified memory cells | Hua-Hsin Yu, Hung-Jen Liao, Hau-Tai Shieh | 2025-06-03 |
| 12300605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei Min Chan | 2025-05-13 |
| 12249391 | Latch type sense amplifier | Hua-Hsin Yu, Hung-Jen Liao, Hau-Tai Shieh | 2025-03-11 |
| 12244311 | Power loss regulation circuit | Je Syu Liu, Chia-Chen Kuo, Yangsyu Lin | 2025-03-04 |
| 12205664 | Memory circuit and method of operating same | Hua-Hsin Yu, Hau-Tai Shieh, Hung-Jen Liao | 2025-01-21 |
| 12183417 | Memory device and manufacturing method of the same | Po-Sheng Wang, Kao-Cheng Lin, Yangsyu Lin, Yen-Huei Chen, Jonathan Tsung-Yung Chang | 2024-12-31 |
| 12170125 | Memory device and electronic device | Chien-Yu Huang, Chia-En Huang, Hua-Tai Shieh | 2024-12-17 |
| 12110741 | Mechanical multiple torque damping device for a horizontal spindle | Lung-Yi CHIANG | 2024-10-08 |
| 12094529 | Was cell for SRAM high-R issue in advanced technology node | Yangsyu Lin, Po-Sheng Wang, Jonathan Tsung-Yung Chang | 2024-09-17 |
| 12072750 | Power management circuit, system-on-chip device, and method of power management | Chia-Chen Kuo, Yangsyu Lin, Yu-Hao Hsu, Hung-Jen Liao | 2024-08-27 |
| 11949799 | I/O circuit design for SRAM-based PUF generators | Jui-Che Tsai, Shih-Lien Linus Lu, Chia-En Huang | 2024-04-02 |
| 11927058 | Blind lifting device and a blind lifting control module thereof | Lung-Yi CHIANG | 2024-03-12 |
| 11923034 | Header circuit placement in memory device | Po-Sheng Wang, Yangsyu Lin, Kao-Cheng Lin, Jonathan Tsung-Yung Chang | 2024-03-05 |
| 11915746 | Memory device with word line pulse recovery | Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang | 2024-02-27 |
| 11915743 | Latch circuit | Hua-Hsin Yu, Hung-Jen Liao, Hau-Tai Shieh | 2024-02-27 |
| 11869623 | Latch type sense amplifier | Hua-Hsin Yu, Hung-Jen Liao, Hau-Tai Shieh | 2024-01-09 |
| 11854970 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei Min Chan | 2023-12-26 |
| 11817144 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Hau-Tai Shieh, Hung-Jen Liao | 2023-11-14 |