Issued Patents All Time
Showing 1–25 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386383 | Memory structure with optimized latch clock design | Ming-Hung Chang, Luping KONG, Jun Xie | 2025-08-12 |
| 12362000 | Memory device and operating method thereof | Jun Liu, Zhi Zhu, Chien-Yu Huang | 2025-07-15 |
| 12362010 | Memory circuit and method of operating same | Luping KONG, Chia-Cheng Chen, Jun Xie | 2025-07-15 |
| 12340871 | Memory circuits with dynamically adjustable pulse widths and methods for operating the same | Ming-Hung Chang, Chia-Cheng Chen, Cheng Hung Lee | 2025-06-24 |
| 12283308 | Memory device and method for operating the same | Kuang Ting Chen, Peijiun Lin, Feng-Ming Chang | 2025-04-22 |
| 12254919 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao | 2025-03-18 |
| 12190984 | Circuit and method of operating the same | Xiu-Li YANG, He-Zhou WAN, Ming-En Bu | 2025-01-07 |
| 12183428 | Memory circuit and method of operating the same | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2024-12-31 |
| 12183432 | Shared decoder circuit and method | XiuLi YANG, He-Zhou WAN, Kuan-Lun Cheng, Luping KONG | 2024-12-31 |
| 12184285 | Latch circuit and memory device | XiuLi YANG, Kuan-Lun Cheng, He-Zhou WAN, Wenchao Hao | 2024-12-31 |
| 12176062 | Memory device | He-Zhou WAN, Xiu-Li YANG, Pei-Le LI | 2024-12-24 |
| 11929109 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao | 2024-03-12 |
| 11811404 | Latch circuit, memory device and method | XiuLi YANG, Kuan-Lun Cheng, He-Zhou WAN, Wenchao Hao | 2023-11-07 |
| 11776622 | Circuit and method of writing to a bit cell | Pankaj Aggarwal, Jaymeen Bharatkumar Aseem | 2023-10-03 |
| 11769539 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Kuan-Lun Cheng | 2023-09-26 |
| 11734142 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Donald George Mikan, Jr., Hao-I Yang +5 more | 2023-08-22 |
| 11721374 | Control circuit of memory device | He-Zhou WAN, Xiu-Li YANG, Pei-Le LI | 2023-08-08 |
| 11715505 | Memory circuit and method of operating the same | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2023-08-01 |
| 11705175 | Shared decoder circuit and method | XiuLi YANG, He-Zhou WAN, Kuan-Lun Cheng, Luping KONG | 2023-07-18 |
| 11705174 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Kuan-Lun Cheng | 2023-07-18 |
| 11670362 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao | 2023-06-06 |
| 11651134 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ming-En Bu, He-Zhou WAN, Hidehiro Fujiwara, Xiu-Li YANG | 2023-05-16 |
| 11545191 | Circuit and method of operating the same | Xiu-Li YANG, He-Zhou WAN, Ming-En Bu | 2023-01-03 |
| 11468929 | Memory circuit and method of operating the same | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2022-10-11 |
| 11450367 | Shared decoder circuit and method | XiuLi YANG, He-Zhou WAN, Kuan-Lun Cheng, Luping KONG | 2022-09-20 |