Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412625 | Static random access memory with adaptive precharge signal generated in response to tracking operation | He-Zhou WAN, Lu-Ping KONG, Wei-Yang Jiang | 2025-09-09 |
| 12211586 | Signal generator for controlling timing of signal in memory device | He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung Chang | 2025-01-28 |
| 12198754 | Timing control circuit of memory device with tracking word line and tracking bit line | Lu-Ping KONG, Kuan-Lun Cheng, He-Zhou WAN | 2025-01-14 |
| 12190940 | Memory device and operating method thereof | He-Zhou WAN, Mu-Yang YE, Yan-Bo SONG | 2025-01-07 |
| 12193206 | Memory device | He-Zhou WAN, Yan-Bo SONG | 2025-01-07 |
| 12190984 | Circuit and method of operating the same | Ching-Wei Wu, He-Zhou WAN, Ming-En Bu | 2025-01-07 |
| 12176062 | Memory device | He-Zhou WAN, Pei-Le LI, Ching-Wei Wu | 2024-12-24 |
| 12002507 | Static random access memory with adaptive precharge signal generated in response to tracking operation | He-Zhou WAN, Lu-Ping KONG, Wei-Yang Jiang | 2024-06-04 |
| 12002542 | Write circuit of memory device and method of operating the same | Kuan-Lun Cheng, He-Zhou WAN, Wei-Yang Jiang | 2024-06-04 |
| 11923041 | Signal generator for controlling timing of signal in memory device | He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung Chang | 2024-03-05 |
| 11862231 | Memory device and operating method thereof | He-Zhou WAN, Mu-Yang YE, Yan-Bo SONG | 2024-01-02 |
| 11769539 | Integrated circuit with asymmetric arrangements of memory arrays | He-Zhou WAN, Kuan-Lun Cheng, Ching-Wei Wu | 2023-09-26 |
| 11735251 | Timing control circuit of memory device with tracking word line and tracking bit line | Lu-Ping KONG, Kuan-Lun Cheng, He-Zhou WAN | 2023-08-22 |
| 11721374 | Control circuit of memory device | He-Zhou WAN, Pei-Le LI, Ching-Wei Wu | 2023-08-08 |
| 11705174 | Integrated circuit with asymmetric arrangements of memory arrays | He-Zhou WAN, Kuan-Lun Cheng, Ching-Wei Wu | 2023-07-18 |
| 11651134 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Hidehiro Fujiwara | 2023-05-16 |
| 11557336 | Static random access memory with adaptive precharge signal generated in response to tracking operation | He-Zhou WAN, Lu-Ping KONG, Wei-Yang Jiang | 2023-01-17 |
| 11545191 | Circuit and method of operating the same | Ching-Wei Wu, He-Zhou WAN, Ming-En Bu | 2023-01-03 |
| 11521662 | Write circuit of memory device | Kuan-Lun Cheng, He-Zhou WAN, Wei-Yang Jiang | 2022-12-06 |
| 11514974 | Memory device | He-Zhou WAN, Mu-Yang YE, Yan-Bo SONG | 2022-11-29 |
| 11462551 | Memory device | He-Zhou WAN, Yan-Bo SONG | 2022-10-04 |
| 11398261 | Method and signal generator for controlling timing of signal in memory device | He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung Chang | 2022-07-26 |
| 11393509 | Control circuit of memory device | He-Zhou WAN, Pei-Le LI, Ching-Wei Wu | 2022-07-19 |
| 11289141 | Integrated circuit with asymmetric arrangements of memory arrays | He-Zhou WAN, Kuan-Lun Cheng, Ching-Wei Wu | 2022-03-29 |
| 11042688 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Hidehiro Fujiwara | 2021-06-22 |