Issued Patents All Time
Showing 1–25 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431192 | Semiconductor device | Nikhil Puri, Venkateswara Reddy Konudula, Teja Masina, Yen-Huei Chen, Hung-Jen Liao | 2025-09-30 |
| 12412621 | Semiconductor device including distributed write driving arrangement | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2025-09-09 |
| 12408316 | Memory array circuit and method of manufacturing same | Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen, Hung-Jen Liao | 2025-09-02 |
| 12387768 | Memory device including separate negative bit line | Chih-Yu Lin, Yi-Hsin Nien, Yen-Huei Chen | 2025-08-12 |
| 12380946 | Memory computation method | Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2025-08-05 |
| 12373131 | Data sequencing circuit and method | Haruki Mori, Wei Zhao | 2025-07-29 |
| 12369292 | Memory device | Yi-Hsin Nien, Chih-Yu Lin, Wei Zhao | 2025-07-22 |
| 12367929 | Memory device having a negative voltage circuit | Yi-Hsin Nien, Chih-Yu Lin, Yen-Huei Chen | 2025-07-22 |
| 12346143 | Voltage regulator with power rail tracking | Haruki Mori, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen +2 more | 2025-07-01 |
| 12334145 | Bitcell supporting bit-write-mask function | Yen-Huei Chen, Yi-Hsin Nien | 2025-06-17 |
| 12308303 | Integrated circuit die with memory macro including through-silicon via and method of forming the same | Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2025-05-20 |
| 12260897 | Separated read BL scheme in 3T dram for read speed improvement | Yi-Hsun Chiu, Yih Wang | 2025-03-25 |
| 12260903 | Memory devices with improved bit line loading | Yi-Hsin Nien, Chih-Yu Lin, Yen-Huei Chen | 2025-03-25 |
| 12260904 | Memory device with additional write bit lines | Chia-En Huang, Yen-Huei Chen, Jui-Che Tsai, Yih Wang | 2025-03-25 |
| 12261152 | Vertical interconnect structures in three-dimensional integrated circuits | Tzu-Hsien Yang, Hiroki Noguchi, Yih Wang | 2025-03-25 |
| 12245412 | SRAM cell word line structure with reduced RC effects | Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao | 2025-03-04 |
| 12230318 | Memory device including a word line with portions with different sizes in different metal layers | Yi-Hsin Nien, Wei Zhao, Chih-Yu Lin, Yen-Huei Chen, Ru-Yu WANG | 2025-02-18 |
| 12164882 | In-memory computation circuit and method | Yu-Der Chih, Yi-Chun Shih, Po-Hao Lee, Yen-Huei Chen, Chia-Fu Lee +1 more | 2024-12-10 |
| 12159688 | Systems and methods for memory operation using local word lines | Yi-Hsin Nien, Yen-Huei Chen | 2024-12-03 |
| 12147784 | Compute in memory | Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Yu-Der Chih, Haruki Mori +1 more | 2024-11-19 |
| 12136466 | Header layout design including backside power rail | Haruki Mori, Chien-Chi TIEN, Chia-En Huang, Yen-Huei Chen, Feng-Lun CHEN | 2024-11-05 |
| 12137548 | Four CPP wide memory cell with buried power grid, and method of fabricating same | Chih-Yu Lin, Yen-Huei Chen, Wei Zhao, Yi-Hsin Nien | 2024-11-05 |
| 12125523 | Memory device and method of manufacturing the same | Yi-Hsin Nien, Chih-Yu Lin, Yen-Huei Chen | 2024-10-22 |
| 12100436 | Method and system to balance ground bounce | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2024-09-24 |
| 12080341 | Memory device including dual control circuits | Yen-Huei Chen | 2024-09-03 |