Issued Patents All Time
Showing 26–50 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12074156 | Memory array circuit and method of manufacturing same | Sahil Preet Singh, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2024-08-27 |
| 12029023 | Memory array circuit and method of manufacturing same | Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen, Hung-Jen Liao | 2024-07-02 |
| 11997843 | 4CPP SRAM cell and array | Chia-En Huang, Yen-Huei Chen, Yih Wang | 2024-05-28 |
| 11989046 | Voltage regulator with power rail tracking | Haruki Mori, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen +2 more | 2024-05-21 |
| 11978723 | Vertical interconnect structures in three-dimensional integrated circuits | Tzu-Hsien Yang, Hiroki Noguchi, Yih Wang | 2024-05-07 |
| 11961554 | Shared power footer circuit | Kao-Cheng Lin, Wei Min Chan, Yen-Huei Chen | 2024-04-16 |
| 11948627 | Static random access memory with write assist circuit | Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2024-04-02 |
| 11935586 | Memory device and method for computing-in-memory (CIM) | Haruki Mori, Wei Zhao | 2024-03-19 |
| 11929116 | Memory device having a negative voltage circuit | Yi-Hsin Nien, Chih-Yu Lin, Yen-Huei Chen | 2024-03-12 |
| 11910587 | Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure | Yi-Hsin Nien, Hung-Jen Liao | 2024-02-20 |
| 11908545 | Memory device and operating method for computing-in-memory | Haruki Mori, Wei Zhao | 2024-02-20 |
| 11854943 | Memory macro including through-silicon via | Tze-Chiang Huang, Hong-Chen Cheng, Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang +2 more | 2023-12-26 |
| 11853596 | Data sequencing circuit and method | Haruki Mori, Wei Zhao | 2023-12-26 |
| 11830543 | Memory computation circuit | Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2023-11-28 |
| 11805636 | Memory device | Yi-Hsin Nien, Chih-Yu Lin, Wei Zhao | 2023-10-31 |
| 11783890 | Semiconductor device including distributed write driving arrangement | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2023-10-10 |
| 11778802 | SRAM cell word line structure with reduced RC effects | Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao | 2023-10-03 |
| 11769533 | Semiconductor chip having memory and logic cells | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2023-09-26 |
| 11715501 | Header layout design including backside power rail | Haruki Mori, Chien-Chi TIEN, Chia-En Huang, Yen-Huei Chen, Feng-Lun CHEN | 2023-08-01 |
| 11714570 | Computing-in-memory device and method | Jonathan Tsung-Yung Chang, Hung-Jen Liao, Yen-Huei Chen, Yih Wang, Haruki Mori | 2023-08-01 |
| 11682440 | Systems and methods for memory operation using local word lines | Yi-Hsin Nien, Yen-Huei Chen | 2023-06-20 |
| 11657870 | Method and system to balance ground bounce | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2023-05-23 |
| 11651134 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Xiu-Li YANG | 2023-05-16 |
| 11637108 | Memory array circuit and method of manufacturing same | Chih-Yu Lin, Hsien-Yu Pan, Yasutoshi Okuno, Yen-Huei Chen, Hung-Jen Liao | 2023-04-25 |
| 11631456 | Bitcell supporting bit-write-mask function | Yen-Huei Chen, Yi-Hsin Nien | 2023-04-18 |