Issued Patents All Time
Showing 76–100 of 136 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11042688 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Xiu-Li YANG | 2021-06-22 |
| 11037644 | Testing circuit, testing method, and apparatus for testing multi-port random access memory | Yen-Huei Chen | 2021-06-15 |
| 11024633 | SRAM cell word line structure with reduced RC effects | Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao | 2021-06-01 |
| 11018142 | Memory cell and method of manufacturing the same | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Yasutoshi Okuno | 2021-05-25 |
| 10991420 | Semiconductor device including distributed write driving arrangement and method of operating same | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2021-04-27 |
| 10978144 | Integrated circuit and operating method thereof | Chia-En Huang, Jui-Che Tsai, Yen-Huei Chen, Yih Wang | 2021-04-13 |
| 10971217 | SRAM cell for interleaved wordline scheme | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2021-04-06 |
| 10964683 | Memory array circuit and method of manufacturing the same | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2021-03-30 |
| 10964389 | Memory cell | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2021-03-30 |
| 10950298 | Mixed threshold voltage memory array | Wei Zhao, Chih-Yu Lin | 2021-03-16 |
| 10943667 | Memory device | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei Zhao | 2021-03-09 |
| 10892008 | Multi word line assertion | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2021-01-12 |
| 10885973 | Memory device and method of controlling memory device | Yen-Huei Chen | 2021-01-05 |
| 10878894 | Memory device having low bitline voltage swing in read port and method for reading memory cell | Haruki Mori, Chih-Yu Lin, Yen-Huei Chen | 2020-12-29 |
| 10872644 | Boost bypass circuitry in a memory storage device | Yen-Huei Chen | 2020-12-22 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2020-12-01 |
| 10839894 | Memory computation circuit and method | Yen-Huei Chen, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-11-17 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2020-11-10 |
| 10783955 | Memory circuit having shared word line | Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao | 2020-09-22 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2020-09-08 |
| 10755768 | Semiconductor device including distributed write driving arrangement and method of operating same | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2020-08-25 |
| 10734066 | Static random access memory with write assist circuit | Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2020-08-04 |
| 10714181 | Memory cell | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2020-07-14 |
| 10706934 | Failure detection circuitry for address decoder for a data storage device | Ching-Wei Wu | 2020-07-07 |
| 10580484 | Semiconductor integrated circuit device | Makoto Yabuuchi | 2020-03-03 |