Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12300312 | Pre-charging bit lines through charge-sharing | Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang | 2025-05-13 |
| 12272420 | Series of parallel sensing operations for multi-level cells | Qing Dong, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang | 2025-04-08 |
| 12260928 | Memory devices with backside boost capacitor and methods for forming the same | Nail Etkin Can Akkaya, Yih Wang, Jonathan Tsung-Yung Chang | 2025-03-25 |
| 12131800 | Physically unclonable cell using dual-interlocking and error correction techniques | Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray | 2024-10-29 |
| 12119052 | Low voltage memory device | Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2024-10-15 |
| 12073869 | Compute in memory system | — | 2024-08-27 |
| 12068284 | Vertical interconnect structures with integrated circuits | Tzu-Hsien Yang, Hiroki Noguchi, Yih Wang | 2024-08-20 |
| 11996163 | Bit line logic circuits and methods | Shang-Chi Wu, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang | 2024-05-28 |
| 11848047 | Pre-charging bit lines through charge-sharing | Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang | 2023-12-19 |
| 11763882 | Low voltage memory device | Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2023-09-19 |
| 11735235 | Series of parallel sensing operations for multi-level cells | Qing Dong, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang | 2023-08-22 |
| 11562779 | Bit line secondary drive circuit and method | Shang-Chi Wu, Yangsyu Lin, Chiting Cheng, Jonathan Tsung-Yung Chang | 2023-01-24 |
| 11404114 | Low voltage memory device | Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2022-08-02 |
| 11322195 | Compute in memory system | — | 2022-05-03 |
| 11238906 | Series of parallel sensing operations for multi-level cells | Qing Dong, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang | 2022-02-01 |
| 11200946 | Low voltage bit-cell | Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin | 2021-12-14 |
| 10971217 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen | 2021-04-06 |
| 10867646 | Bit line logic circuits and methods | Shang-Chi Wu, Chiting Cheng, Jonathan Tsung-Yung Chang, Yangsyu Lin | 2020-12-15 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2020-12-01 |
| 10847214 | Low voltage bit-cell | Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Yen-Ting Lin | 2020-11-24 |
| 10847217 | Pre-charging bit lines through charge-sharing | Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang | 2020-11-24 |
| 10803928 | Low voltage memory device | Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang | 2020-10-13 |
| 10770131 | SRAM cell for interleaved wordline scheme | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen | 2020-09-08 |
| 10510403 | Memory read stability enhancement with short segmented bit line architecture | Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen, Sahil Preet Singh | 2019-12-17 |
| 10410715 | Pre-charging bit lines through charge-sharing | Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang | 2019-09-10 |