Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272427 | Semiconductor device including first and second clock generators | Jaspal Singh Shah, Atul Katoch | 2025-04-08 |
| 12217792 | Memory circuit and method of operating same | Atul Katoch | 2025-02-04 |
| 12165739 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Atul Katoch | 2024-12-10 |
| 12074156 | Memory array circuit and method of manufacturing same | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2024-08-27 |
| D1024304 | Air purifier | — | 2024-04-23 |
| 11948627 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2024-04-02 |
| 11922998 | Memory device with global and local latches | Atul Katoch | 2024-03-05 |
| 11830544 | Write assist for a memory device and methods of forming the same | Yen-Huei Chen, Hung-Jen Liao | 2023-11-28 |
| 11763863 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Atul Katoch | 2023-09-19 |
| 11423977 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2022-08-23 |
| 11423978 | Write assist for a memory device and methods of forming the same | Yen-Huei Chen, Hung-Jen Liao | 2022-08-23 |
| 11361818 | Memory device with global and local latches | Atul Katoch | 2022-06-14 |
| 11309000 | Systems and methods for controlling power management operations in a memory device | Sanjeev Kumar Jain, Atul Katoch | 2022-04-19 |
| 11145655 | Memory device with reduced-resistance interconnect | Yen-Huei Chen | 2021-10-12 |
| 11120868 | Semiconductor memory device using shared data line for read/write operation | Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao +3 more | 2021-09-14 |
| 10991423 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying | 2021-04-27 |
| 10971220 | Write assist for a memory device and methods of forming the same | Yen-Huei Chen, Hung-Jen Liao | 2021-04-06 |
| 10964683 | Memory array circuit and method of manufacturing the same | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen | 2021-03-30 |
| 10854282 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2020-12-01 |
| 10832765 | Variation tolerant read assist circuit for SRAM | Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen | 2020-11-10 |
| 10790015 | Flying and twisted bit line architecture for dual-port static random-access memory (DP SRAM) | Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying | 2020-09-29 |
| 10734066 | Static random access memory with write assist circuit | Hidehiro Fujiwara, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao | 2020-08-04 |
| 10535658 | Memory device with reduced-resistance interconnect | Yen-Huei Chen | 2020-01-14 |
| 10529415 | Write assist for a memory device and methods of forming the same | Yen-Huei Chen, Hung-Jen Liao | 2020-01-07 |
| 10510403 | Memory read stability enhancement with short segmented bit line architecture | Mahmut Sinangil, Hidehiro Fujiwara, Hung-Jen Liao, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2019-12-17 |