Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400689 | Circuits and methods of mitigating hold time failure of pipeline for memory device | — | 2025-08-26 |
| 12379740 | Technique to mitigate clock generation failure at high input clock slew | Atul Katoch | 2025-08-05 |
| 12272427 | Semiconductor device including first and second clock generators | Sahil Preet Singh, Atul Katoch | 2025-04-08 |
| 12243602 | Method, device, and circuit for high-speed memories | Atul Katoch | 2025-03-04 |
| 12136454 | Memory device having a comparator circuit | Atul Katoch | 2024-11-05 |
| 12119079 | Circuits and methods of mitigating hold time failure of pipeline for memory device | — | 2024-10-15 |
| 11894086 | Method, device, and circuit for high-speed memories | Atul Katoch | 2024-02-06 |
| 11398271 | Memory device having a comparator circuit | Atul Katoch | 2022-07-26 |
| 11176972 | Memory power management | Sanjeev Kumar Jain | 2021-11-16 |
| 10964381 | Write assist circuit of memory device | — | 2021-03-30 |
| 10770136 | Write assist circuit of memory device | — | 2020-09-08 |
| 10762931 | Memory power management | Sanjeev Kumar Jain | 2020-09-01 |
| 10510404 | Write assist circuit of memory device | — | 2019-12-17 |
| 10269418 | Write assist circuit of memory device | — | 2019-04-23 |
| 10102901 | Write assist circuit of memory device | — | 2018-10-16 |
| 9542995 | Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs | Manoj Sachdev | 2017-01-10 |
| 8488403 | Sense-amplification with offset cancellation for static random access memories | Manoj Sachdev, Mohammad Sharifkhani, David Rennie | 2013-07-16 |