Issued Patents All Time
Showing 1–25 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412605 | Bit line pre-charge circuit and method | Che-Ju Yeh, Yu-Hao Hsu, Cheng Hung Lee | 2025-09-09 |
| 12400708 | Memory device and method for reducing active power consumption thereof using address control | Chien-Yuan Chen, Cheng Hung Lee | 2025-08-26 |
| 12400723 | Latch type sense amplifier for testing | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-08-26 |
| 12354647 | Memory device sense amplifier control | Chien-Yuan Chen, Cheng Hung Lee | 2025-07-08 |
| 12347483 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2025-07-01 |
| 12322438 | Latch circuit formed by modified memory cells | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-06-03 |
| 12300605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Wei Min Chan | 2025-05-13 |
| 12254919 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao | 2025-03-18 |
| 12249391 | Latch type sense amplifier | Hua-Hsin Yu, Hung-Jen Liao, Cheng Hung Lee | 2025-03-11 |
| 12230632 | Integrated circuit layout and method thereof | Chien-Yuan Chen | 2025-02-18 |
| 12205664 | Memory circuit and method of operating same | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2025-01-21 |
| 12183428 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2024-12-31 |
| 12068018 | Power mode wake-up for memory on different power domains | Che-Ju Yeh, Yi-Tzu Chen | 2024-08-20 |
| 11989498 | FinFET semiconductor device grouping | Yi-Tzu Chen, Che-Ju Yeh | 2024-05-21 |
| 11929109 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao | 2024-03-12 |
| 11915743 | Latch circuit | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2024-02-27 |
| 11869623 | Latch type sense amplifier | Hua-Hsin Yu, Hung-Jen Liao, Cheng Hung Lee | 2024-01-09 |
| 11854970 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Wei Min Chan | 2023-12-26 |
| 11817144 | Arrangements of memory devices and methods of operating the memory devices | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2023-11-14 |
| 11763873 | Power mode wake-up for memory on different power domains | Che-Ju Yeh, Yi-Tzu Chen | 2023-09-19 |
| 11715505 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2023-08-01 |
| 11682453 | Word line pulse width control circuit in static random access memory | Anjana Singh, Cheng Hung Lee, Yi-Tzu Chen | 2023-06-20 |
| 11670362 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao | 2023-06-06 |
| 11568121 | FinFET semiconductor device grouping | Yi-Tzu Chen, Che-Ju Yeh | 2023-01-31 |
| 11468929 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao, Fu-An Wu, He-Zhou WAN +1 more | 2022-10-11 |