Issued Patents All Time
Showing 26–50 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11450605 | Reducing internal node loading in combination circuits | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Kao-Cheng Lin, Wei Min Chan | 2022-09-20 |
| 11444608 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2022-09-13 |
| 11423962 | Bit line pre-charge circuit and method | Che-Ju Yeh, Yu-Hao Hsu, Cheng Hung Lee | 2022-08-23 |
| 11361810 | Power mode wake-up for memory on different power domains | Che-Ju Yeh, Yi-Tzu Chen | 2022-06-14 |
| 11361812 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Ching-Wei Wu, Hung-Jen Liao | 2022-06-14 |
| 11302701 | Three-dimensional static random access memory device structures | Chien-Yu Huang, Chien-Yuan Chen | 2022-04-12 |
| 11264081 | Memory circuit, electronic device having the memory circuit, and method of operating memory circuit | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2022-03-01 |
| 11217301 | High speed memory device implementing a plurality of supply voltages | Hua-Hsin Yu | 2022-01-04 |
| 11120868 | Semiconductor memory device using shared data line for read/write operation | Chien-Yuan Chen, Che-Ju Yeh, Cheng Hung Lee, Hung-Jen Liao, Sahil Preet Singh +3 more | 2021-09-14 |
| 11057025 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2021-07-06 |
| 11056182 | Word line pulse width control circuit in static random access memory | Anjana Singh, Cheng Hung Lee, Yi-Tzu Chen | 2021-07-06 |
| 10950296 | Latch circuit formed from bit cell | Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao | 2021-03-16 |
| 10878890 | Operation assist circuit, memory device and operation assist method | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2020-12-29 |
| 10878934 | Memory device and electronic device | Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee | 2020-12-29 |
| 10778198 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2020-09-15 |
| 10756094 | Three-dimensional static random access memory device structures | Chien-Yu Huang, Chien-Yuan Chen | 2020-08-25 |
| 10658026 | Word line pulse width control circuit in static random access memory | Anjana Singh, Cheng Hung Lee, Yi-Tzu Chen | 2020-05-19 |
| 10651832 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao | 2020-05-12 |
| 10614878 | High speed SRAM device with cross coupled bit line charging circuit and voltage | Hua-Hsin Yu | 2020-04-07 |
| 10510401 | Semiconductor memory device using shared data line for read/write operation | Chien-Yuan Chen, Che-Ju Yeh, Cheng Hung Lee, Hung-Jen Liao, Sahil Preet Singh +3 more | 2019-12-17 |
| 10354719 | 3D structure for advanced SRAM design to avoid half-selected issue | Chien-Yuan Chen, Chien-Yu Huang | 2019-07-16 |
| 10163489 | 3D structure for advanced SRAM design to avoid half-selected issue | Chien-Yuan Chen, Chien-Yu Huang | 2018-12-25 |
| 9979399 | Level shifter | Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Che-Ju Yeh | 2018-05-22 |
| 9941287 | Three-dimensional static random access memory device structures | Chien-Yu Huang, Chien-Yuan Chen | 2018-04-10 |
| 9928888 | Low power consumption memory device | Yi-Tzu Chen, Anjana Singh, Che-Ju Yeh | 2018-03-27 |