Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412625 | Static random access memory with adaptive precharge signal generated in response to tracking operation | Xiu-Li YANG, Lu-Ping KONG, Wei-Yang Jiang | 2025-09-09 |
| 12211586 | Signal generator for controlling timing of signal in memory device | Xiu-Li YANG, Mu-Yang YE, Lu-Ping KONG, Ming-Hung Chang | 2025-01-28 |
| 12198754 | Timing control circuit of memory device with tracking word line and tracking bit line | Xiu-Li YANG, Lu-Ping KONG, Kuan-Lun Cheng | 2025-01-14 |
| 12190940 | Memory device and operating method thereof | Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG | 2025-01-07 |
| 12193206 | Memory device | Xiu-Li YANG, Yan-Bo SONG | 2025-01-07 |
| 12190984 | Circuit and method of operating the same | Xiu-Li YANG, Ching-Wei Wu, Ming-En Bu | 2025-01-07 |
| 12183428 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu +1 more | 2024-12-31 |
| 12183432 | Shared decoder circuit and method | XiuLi YANG, Ching-Wei Wu, Kuan-Lun Cheng, Luping KONG | 2024-12-31 |
| 12184285 | Latch circuit and memory device | XiuLi YANG, Kuan-Lun Cheng, Ching-Wei Wu, Wenchao Hao | 2024-12-31 |
| 12176062 | Memory device | Xiu-Li YANG, Pei-Le LI, Ching-Wei Wu | 2024-12-24 |
| 12080372 | System and method of power management in memory design | XiuLi YANG, Ming-En Bu, Mengxiang XU, Zong-Liang CAO | 2024-09-03 |
| 12002507 | Static random access memory with adaptive precharge signal generated in response to tracking operation | Xiu-Li YANG, Lu-Ping KONG, Wei-Yang Jiang | 2024-06-04 |
| 12002542 | Write circuit of memory device and method of operating the same | Xiu-Li YANG, Kuan-Lun Cheng, Wei-Yang Jiang | 2024-06-04 |
| 11923041 | Signal generator for controlling timing of signal in memory device | Xiu-Li YANG, Mu-Yang YE, Lu-Ping KONG, Ming-Hung Chang | 2024-03-05 |
| 11862231 | Memory device and operating method thereof | Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG | 2024-01-02 |
| 11811404 | Latch circuit, memory device and method | XiuLi YANG, Kuan-Lun Cheng, Ching-Wei Wu, Wenchao Hao | 2023-11-07 |
| 11769539 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, Kuan-Lun Cheng, Ching-Wei Wu | 2023-09-26 |
| 11735251 | Timing control circuit of memory device with tracking word line and tracking bit line | Xiu-Li YANG, Lu-Ping KONG, Kuan-Lun Cheng | 2023-08-22 |
| 11721374 | Control circuit of memory device | Xiu-Li YANG, Pei-Le LI, Ching-Wei Wu | 2023-08-08 |
| 11715505 | Memory circuit and method of operating the same | Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu +1 more | 2023-08-01 |
| 11705175 | Shared decoder circuit and method | XiuLi YANG, Ching-Wei Wu, Kuan-Lun Cheng, Luping KONG | 2023-07-18 |
| 11705174 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, Kuan-Lun Cheng, Ching-Wei Wu | 2023-07-18 |
| 11651134 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, Hidehiro Fujiwara, Xiu-Li YANG | 2023-05-16 |
| 11557336 | Static random access memory with adaptive precharge signal generated in response to tracking operation | Xiu-Li YANG, Lu-Ping KONG, Wei-Yang Jiang | 2023-01-17 |
| 11545191 | Circuit and method of operating the same | Xiu-Li YANG, Ching-Wei Wu, Ming-En Bu | 2023-01-03 |