Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387768 | Memory device including separate negative bit line | Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen | 2025-08-12 |
| 12367929 | Memory device having a negative voltage circuit | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen | 2025-07-22 |
| 12369292 | Memory device | Chih-Yu Lin, Wei Zhao, Hidehiro Fujiwara | 2025-07-22 |
| 12334145 | Bitcell supporting bit-write-mask function | Hidehiro Fujiwara, Yen-Huei Chen | 2025-06-17 |
| 12260903 | Memory devices with improved bit line loading | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen | 2025-03-25 |
| 12230318 | Memory device including a word line with portions with different sizes in different metal layers | Wei Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu WANG | 2025-02-18 |
| 12159688 | Systems and methods for memory operation using local word lines | Hidehiro Fujiwara, Yen-Huei Chen | 2024-12-03 |
| 12137548 | Four CPP wide memory cell with buried power grid, and method of fabricating same | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2024-11-05 |
| 12125523 | Memory device and method of manufacturing the same | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen | 2024-10-22 |
| 11929116 | Memory device having a negative voltage circuit | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen | 2024-03-12 |
| 11910587 | Memory circuit having SRAM memory cells and method for forming a SRAM memory cell structure | Hidehiro Fujiwara, Hung-Jen Liao | 2024-02-20 |
| 11805636 | Memory device | Chih-Yu Lin, Wei Zhao, Hidehiro Fujiwara | 2023-10-31 |
| 11682440 | Systems and methods for memory operation using local word lines | Hidehiro Fujiwara, Yen-Huei Chen | 2023-06-20 |
| 11631456 | Bitcell supporting bit-write-mask function | Hidehiro Fujiwara, Yen-Huei Chen | 2023-04-18 |
| 11569246 | Four CPP wide memory cell with buried power grid, and method of fabricating same | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2023-01-31 |
| 11562786 | Memory device having a negative voltage circuit | Hidehiro Fujiwara, Chih-Yu Lin, Yen-Huei Chen | 2023-01-24 |
| 11404113 | Memory device including a word line with portions with different sizes in different metal layers | Wei Zhao, Chih-Yu Lin, Hidehiro Fujiwara, Yen-Huei Chen, Ru-Yu WANG | 2022-08-02 |
| 11264070 | Systems and methods for memory operation using local word lines | Hidehiro Fujiwara, Yen-Huei Chen | 2022-03-01 |
| 11183234 | Bitcell supporting bit-write-mask function | Hidehiro Fujiwara, Yen-Huei Chen | 2021-11-23 |