Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11393509 | Control circuit of memory device | He-Zhou WAN, Xiu-Li YANG, Pei-Le LI | 2022-07-19 |
| 11361812 | Sub-word line driver placement for memory device | Yi-Tzu Chen, Hau-Tai Shieh, Hung-Jen Liao | 2022-06-14 |
| 11325145 | System for determining spraying information used for spraying a three-dimensional object | Yu-Fong Yang, Yen-Te Lee, Wei-Hsin Hsu | 2022-05-10 |
| 11289154 | Circuit and method of writing to a bit cell | Pankaj Aggarwal, Jaymeen Bharatkumar Aseem | 2022-03-29 |
| 11289141 | Integrated circuit with asymmetric arrangements of memory arrays | Xiu-Li YANG, He-Zhou WAN, Kuan-Lun Cheng | 2022-03-29 |
| 11256588 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Donald George Mikan, Jr., Hao-I Yang +5 more | 2022-02-22 |
| 11190169 | Latch circuit, memory device and method | XiuLi YANG, Kuan-Lun Cheng, He-Zhou WAN, Wenchao Hao | 2021-11-30 |
| 11189342 | Memory macro and method of operating the same | Pankaj Aggarwal, Jui-Che Tsai | 2021-11-30 |
| 11139040 | Method of detecting address decoding error | Hidehiro Fujiwara, Chun-Hao Chang | 2021-10-05 |
| 11042688 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ming-En Bu, He-Zhou WAN, Hidehiro Fujiwara, Xiu-Li YANG | 2021-06-22 |
| 10937477 | Shared decoder circuit and method | XiuLi YANG, He-Zhou WAN, Kuan-Lun Cheng, Luping KONG | 2021-03-02 |
| 10770135 | Memory macro which changes operational modes | Pankaj Aggarwal, Jui-Che Tsai | 2020-09-08 |
| 10755770 | Circuit and method for writing to a bit cell | Pankaj Aggarwal, Jaymeen Bharatkumar Aseem | 2020-08-25 |
| 10706934 | Failure detection circuitry for address decoder for a data storage device | Hidehiro Fujiwara | 2020-07-07 |
| 10705934 | Scan synchronous-write-through testing architectures for a memory device | Ming-Hung Chang, Atul Katoch, Chia-En Huang, Donald George Mikan, Jr., Hao-I Yang +5 more | 2020-07-07 |
| 10553300 | Method of detecting address decoding error and address decoder error detection system | Hidehiro Fujiwara, Chun-Hao Chang | 2020-02-04 |
| 10354731 | Failure detection circuitry for address decoder for a data storage device | Hidehiro Fujiwara | 2019-07-16 |
| 10186313 | Memory macro disableable input-output circuits and methods of operating the same | Pankaj Aggarwal, Jui-Che Tsai | 2019-01-22 |
| 10141059 | Failure detection circuitry for address decoder for a data storage device | Hidehiro Fujiwara | 2018-11-27 |
| 10090032 | Word line driving unit with a boost voltage generator and memory device including the same | Ming-En Bu, He-Zhou WAN, Weiyang Jiang | 2018-10-02 |
| 10083739 | Three-dimensional three-port bit cell and method of assembling same | Tzu-Kuei Lin, Hung-Jen Liao, Yen-Huei Chen | 2018-09-25 |
| 9851915 | Two-stage read/write 3D architecture for memory devices | Kuang Ting Chen | 2017-12-26 |
| 9690510 | Two-stage read/write 3D architecture for memory devices | Kuang Ting Chen | 2017-06-27 |
| 9666302 | System and method for memory scan design-for-test | Ming-Hung Chang, Chia-Cheng Chen | 2017-05-30 |
| 9589885 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Jui-Che Tsai, Hong-Chen Cheng +1 more | 2017-03-07 |