Issued Patents All Time
Showing 51–75 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9490005 | Memory circuit and method for routing the memory circuit | Cheng Hung Lee, Jui-Che Tsai, Kuang Ting Chen | 2016-11-08 |
| 9490006 | Time division multiplexed multiport memory | XiuLi YANG, He-Zhou WAN, Ming-En Bu, Mu-Jen Huang | 2016-11-08 |
| 9455025 | Static random access memory and method of controlling the same | Ming-Hung Chang, Chia-Cheng Chen | 2016-09-27 |
| 9281311 | Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same | Wei-Shuo Kao, Chia-Cheng Chen, Kuang Ting Chen | 2016-03-08 |
| 9275724 | Method of writing to and reading data from a three-dimensional two port register file | Jui-Che Tsai | 2016-03-01 |
| 9275752 | Read-only memory | Kuang Ting Chen | 2016-03-01 |
| 9245615 | Boost system for dual-port SRAM | He-Zhou WAN, Ming-En Bu, XiuLi YANG, Cheng Hung Lee, Mu-Jen Huang | 2016-01-26 |
| 9230622 | Simultaneous two/dual port access on 6T SRAM | Chia-Cheng Chen, Kuang Ting Chen, Wei-Shuo Kao, Jui-Che Tsai | 2016-01-05 |
| 9183907 | Vccmin for a dual port synchronous random access memory (DPSRAM) cell utilized as a single port synchronous random access memory (SPSRAM) cell | Cheng Hung Lee, Chia-Cheng Chen | 2015-11-10 |
| 9129956 | Device having multiple-layer pins in memory MUX1 layout | Hung-Jen Liao, Jung-Hsuan Chen, Chien-Chi TIEN, Jui-Che Tsai, Hong-Chen Cheng +1 more | 2015-09-08 |
| 9064604 | Timing logic for memory array | Harn-Bor Yang, Chia-Cheng Chen | 2015-06-23 |
| 9001611 | Three-dimensional two port register file | Jui-Che Tsai | 2015-04-07 |
| 8845247 | Thermal compensation system for a milling machine | Ying-Shing Shiao, Chia-Hui Tang, Yu-Che Wang, Paul Chang | 2014-09-30 |
| 8837192 | N-bit rom cell | Kuang Ting Chen, Cheng Hung Lee | 2014-09-16 |
| 8675435 | Asymmetric sense amplifier design | Kuang Ting Chen, Cheng Hung Lee | 2014-03-18 |
| 8565009 | Access to multi-port devices | Lee Cheng Hung, Hung-Je Liao, Jui-Che Tsai | 2013-10-22 |
| 8488395 | Keepers, integrated circuits, and systems thereof | Cheng Hung Lee, Bin Sheng, Hung-Jen Liao | 2013-07-16 |
| 8437210 | Asymmetric sense amplifier design | Kuang Ting Chen, Cheng Hung Lee | 2013-05-07 |
| 8411479 | Memory circuits, systems, and methods for routing the memory circuits | Cheng Hung Lee, Jui-Che Tsai, Kuang Ting Chen | 2013-04-02 |
| 8406058 | Read only memory and operating method thereof | Cheng Hung Lee, He-Zhou WAN, Wei-Yang Jiang | 2013-03-26 |
| 8395950 | Memory device having a clock skew generator | Tzu-Kuei Lin, Hung-Jen Liao, Shao-Yu Chou | 2013-03-12 |
| 8305791 | Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof | Cheng Hung Lee, Li-Chen Chen, Weiyang Jiang | 2012-11-06 |
| 7952911 | SRAM cell array structure | Cheng Hung Lee, Hung-Jen Liao | 2011-05-31 |
| 7613054 | SRAM device with enhanced read/write operations | Cheng Hung Lee, Ping-Wei Wang, Shu-Hsuan Lin, Feng-Ming Chang, Hung-Jen Liao | 2009-11-03 |
| 7502277 | Word-line driver design for pseudo two-port memories | Cheng Hung Lee, Hung-Jen Liao | 2009-03-10 |