Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11263375 | Constraint determination system and method for semiconductor circuit | Shi-Wen TAN, Szu-Ju Huang, Shih Feng Hong | 2022-03-01 |
| 11114376 | System for layout design of structure with inter layer vias | Ching-Fang Chen, Jia-Jye Shen | 2021-09-07 |
| 11093681 | Method and system for generating layout design of integrated circuit | Shih-Yao Lin, Yin-An Chen, Shih Feng Hong | 2021-08-17 |
| 11087066 | Static voltage drop (SIR) violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2021-08-10 |
| 11017149 | Machine-learning design enablement platform | Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee | 2021-05-25 |
| 10943049 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2021-03-09 |
| 10922466 | Cell layout of semiconductor device | Huang-Yu Chen, Yun-Han Lee | 2021-02-16 |
| 10810346 | Static voltage drop (SIR) violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2020-10-20 |
| 10678973 | Machine-learning design enablement platform | Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee | 2020-06-09 |
| 10566278 | Method for layout design and structure with inter-layer vias | Ching-Fang Chen, Jia-Jye Shen | 2020-02-18 |
| 10268795 | Method and system for timing optimization with detour prediction | Chih-Tien Chang, Kuan-Hua Su, Szu-Ju Huang | 2019-04-23 |
| 10162925 | Cell layout of semiconductor device | Huang-Yu Chen, Yun-Han Lee | 2018-12-25 |
| 9679840 | Method for layout design and structure with inter-layer vias | Ching-Fang Chen, Jia-Jye Shen | 2017-06-13 |
| 9601478 | Oxide definition (OD) gradient reduced semiconductor device | Chun-Cheng Ku, Chin-Her Chien, Wei-Pin Changchien | 2017-03-21 |
| 9478469 | Integrated circuit comprising buffer chain | Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng | 2016-10-25 |
| 9471742 | Method for displaying timing information of an integrated circuit floorplan in real time | Huang-Yu Chen, Yun-Han Lee | 2016-10-18 |
| 9286431 | Oxide definition (OD) gradient reduced semiconductor device and method of making | Chun-Cheng Ku, Chin-Her Chien, Wei-Pin Changchien | 2016-03-15 |
| 9275176 | Register clustering for clock network topology generation | — | 2016-03-01 |
| 8981842 | Integrated circuit comprising buffer chain | Chien-Hui Chen, Wei-Pin Changchien, Chin-Her Chien, Nan-Hsin Tseng | 2015-03-17 |
| 8898608 | Method for displaying timing information of an integrated circuit floorplan | Huang-Yu Chen, Yun-Han Lee | 2014-11-25 |
| 8887117 | Register clustering for clock network topology generation | — | 2014-11-11 |
| 8863062 | Methods and apparatus for floorplanning and routing co-design | Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee | 2014-10-14 |
| 8707238 | Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs | Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee +1 more | 2014-04-22 |
| 8701070 | Group bounding box region-constrained placement for integrated circuit design | Chun-Cheng Ku, Yun-Han Lee, Shao-Yu Wang, Wei-Pin Changchien, Chin-Chou Liu | 2014-04-15 |