Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424515 | SOIC chip architecture | Fong-Yuan Chang, Chin-Chou Liu, Cheng-Hung Yeh, Hui Yu Lee, Po-Hsiang Huang +1 more | 2025-09-23 |
| 12223252 | Through-silicon via in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2025-02-11 |
| 12154842 | Heat dissipation structures for three-dimensional system on integrated chip structure | Po-Hsiang Huang, Chin-Chou Liu, Fong-Yuan Chang, Hui Yu Lee | 2024-11-26 |
| 12027513 | Layout design methodology for stacked devices | Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Ka Fai Chang | 2024-07-02 |
| 11756951 | Layout design methodology for stacked devices | Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu, Ka Fai Chang | 2023-09-12 |
| 11749584 | Heat dissipation structures | Po-Hsiang Huang, Chin-Chou Liu, Fong-Yuan Chang, Hui Yu Lee | 2023-09-05 |
| 11715668 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Chou Liu, Yun-Han Lee | 2023-08-01 |
| 11586797 | Through-silicon vias in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2023-02-21 |
| 11387177 | Package structure and method for forming the same | Po-Hsiang Huang, Cheng-Hung Yeh, TAI-YU WANG, MING-KE TSAI, Yao-Hsien Tsai +6 more | 2022-07-12 |
| 11367695 | Interposer with capacitors | Fong-Yuan Chang, Cheng-Hung Yeh, Hsiang-Ho Chang, Po-Hsiang Huang, Sheng-Hsiung Chen +4 more | 2022-06-21 |
| 11222884 | Layout design methodology for stacked devices | Fong-Yuan Chang, Chin-Chou Liu, Po-Hsiang Huang, Ka Fai Chang | 2022-01-11 |
| 11211333 | Through silicon via optimization for three-dimensional integrated circuits | Fong-Yuan Chang, Chin-Chou Liu, Po-Hsiang Huang, Noor Mohamed Ettuveettil | 2021-12-28 |
| 11094608 | Heat dissipation structure including stacked chips surrounded by thermal interface material rings | Po-Hsiang Huang, Chin-Chou Liu, Fong-Yuan Chang, Hui Yu Lee | 2021-08-17 |
| 11075116 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Chou Liu, Yun-Han Lee | 2021-07-27 |
| 10949597 | Through-silicon vias in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2021-03-16 |
| 10692763 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Chou Liu, Yun-Han Lee | 2020-06-23 |
| 10163708 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Chou Liu, Yun-Han Lee | 2018-12-25 |
| 9847318 | Monolithic stacked integrated circuits with a redundant layer for repairing defects | Kuan-Yu Lin, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien | 2017-12-19 |
| 9779990 | Integrated antenna on interposer substrate | Bo-Jr Huang, William Wu Shen, Chin-Chou Liu, Yun-Han Lee | 2017-10-03 |
| 9601478 | Oxide definition (OD) gradient reduced semiconductor device | Yi-Lin Chuang, Chun-Cheng Ku, Wei-Pin Changchien | 2017-03-21 |
| 9478469 | Integrated circuit comprising buffer chain | Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Nan-Hsin Tseng | 2016-10-25 |
| 9286431 | Oxide definition (OD) gradient reduced semiconductor device and method of making | Yi-Lin Chuang, Chun-Cheng Ku, Wei-Pin Changchien | 2016-03-15 |
| 9269640 | Repairing monolithic stacked integrated circuits with a redundant layer and lithography process | Kuan-Yu Lin, Jung-Rung Jiang, Ji-Jan Chen, Wei-Pin Changchien | 2016-02-23 |
| 8981842 | Integrated circuit comprising buffer chain | Yi-Lin Chuang, Chien-Hui Chen, Wei-Pin Changchien, Nan-Hsin Tseng | 2015-03-17 |