Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424515 | SOIC chip architecture | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Hui Yu Lee, Po-Hsiang Huang +1 more | 2025-09-23 |
| 12223252 | Through-silicon via in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2025-02-11 |
| 11694973 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng +1 more | 2023-07-04 |
| 11586797 | Through-silicon vias in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2023-02-21 |
| 11387177 | Package structure and method for forming the same | Chin-Her Chien, Po-Hsiang Huang, TAI-YU WANG, MING-KE TSAI, Yao-Hsien Tsai +6 more | 2022-07-12 |
| 11367695 | Interposer with capacitors | Fong-Yuan Chang, Hsiang-Ho Chang, Po-Hsiang Huang, Chin-Her Chien, Sheng-Hsiung Chen +4 more | 2022-06-21 |
| 11088084 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng +1 more | 2021-08-10 |
| 10949597 | Through-silicon vias in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Sen-Bor Jan +2 more | 2021-03-16 |
| 10665550 | Electromagnetic shielding metal-insulator-metal capacitor structure | Hui Yu Lee, Chin-Chou Liu, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng +1 more | 2020-05-26 |
| 9666490 | Multi-layer semiconductor structures for fabricating inverter chains | I-Fan Lin, Yi-Tang Lin, Hsien-Hsin Sean Lee, Chou-Kun Lin | 2017-05-30 |
| 9373623 | Multi-layer semiconductor structures for fabricating inverter chains | I-Fan Lin, Yi-Tang Lin, Hsien-Hsin Sean Lee, Chou-Kun Lin | 2016-06-21 |
| 9330215 | Method and system for verifying the design of an integrated circuit having multiple tiers | Yao-Hsien Tsai, Chi-Ting Huang, Hsien-Hsin Sean Lee | 2016-05-03 |
| 9104835 | Systems and methods for determining effective capacitance to facilitate a timing analysis | Chao-Yang Yeh, Chi-Ting Huang | 2015-08-11 |
| 8910101 | Systems and methods for determining effective capacitance to facilitate a timing analysis | Chao-Yang Yeh, Chi-Ting Huang | 2014-12-09 |
| 8826207 | Method of generating technology file for integrated circuit design tools | Cliff Hou, Gwan Sin Chang, Chih-Tsung Yao | 2014-09-02 |
| 8707230 | Method and system for semiconductor simulation | Wei Hu, Chin-Cheng Kuo, Jui-Feng Kuan, Yi-Kan Cheng | 2014-04-22 |
| 8119310 | Mask-shift-aware RC extraction for double patterning design | Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Dian-Hau Chen +2 more | 2012-02-21 |
| 7904844 | System, method, and computer program product for matching cell layout of an integrated circuit design | Gwan Sin Chang, Feng-Ming Chang, Ping-Wei Wang | 2011-03-08 |
| 7788612 | System, method, and computer program product for matching cell layout of an integrated circuit design | Gwan Sin Chang, Feng-Ming Chang, Ping-Wei Wang | 2010-08-31 |