Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8826207 | Method of generating technology file for integrated circuit design tools | Gwan Sin Chang, Cheng-Hung Yeh, Chih-Tsung Yao | 2014-09-02 |
| 8352888 | Model import for electronic design automation | Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin +1 more | 2013-01-08 |
| 8214772 | Model import for electronic design automation | Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin +1 more | 2012-07-03 |
| 8037575 | Method for shape and timing equivalent dimension extraction | Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu +4 more | 2011-10-18 |
| 7994606 | De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits | Lee-Chung Lu, Chia-Lin Cheng | 2011-08-09 |
| 7954072 | Model import for electronic design automation | Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin +1 more | 2011-05-31 |
| 7801717 | Method for smart dummy insertion to reduce run time and dummy count | Gwan Sin Chang, Yi-Kan Cheng | 2010-09-21 |
| 7797646 | Method for using mixed multi-Vt devices in a cell-based design | Shine C. Chung, Kun-Lung Chen, Lee-Chung Lu | 2010-09-14 |
| 7793130 | Mother/daughter switch design with self power-up control | Shih-Hsien Yang, Chung-Hsing Wang, Lee-Chung Lu, Chun-Hui Tai | 2010-09-07 |
| 7783999 | Electrical parameter extraction for integrated circuit design | Tsong-Hua Ou, Ying-Chou Cheng, Chia-Chi Lin, Ru-Gun Liu, Chih-Ming Lai +3 more | 2010-08-24 |
| 7685558 | Method for detection and scoring of hot spots in a design layout | Chih-Ming Lai, Ru-Gun Liu, I-Chang Shin, Yao-Ching Ku | 2010-03-23 |
| 7640520 | Design flow for shrinking circuits having non-shrinkable IP layout | Chung-Hsing Wang, Lee-Chung Lu, Lie-Szu Juang | 2009-12-29 |
| 7281230 | Method of using mixed multi-Vt devices in a cell-based design | Shine C. Chung, Kun-Lung Chen, Lee-Chung Lu | 2007-10-09 |
| 7262951 | De-coupling capacitors produced by utilizing dummy conductive structures integrated circuits | Lee-Chung Lu, Chia-Lin Cheng | 2007-08-28 |
| 7247894 | Very fine-grain voltage island integrated circuit | Li-Chun Tien, Ching-Hao Shaw, Wan-Pin Yu, Chia-Lin Cheng, Lee-Chung Lu | 2007-07-24 |
| 7017132 | Methodology to optimize hierarchical clock skew by clock delay compensation | Chia-Lin Cheng, Lee-Chung Lu | 2006-03-21 |
| 6862723 | Methodology of generating antenna effect models for library/IP in VLSI physical design | Chung-Hsing Wang, Daisy Wang, Chia-Ling Cheng, Lee-Chung Lu | 2005-03-01 |
| 6797999 | Flexible routing channels among vias | Lee-Chung Lu, Chia-Lin Cheng | 2004-09-28 |
| 6789248 | Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization | Lee-Chung Lu, Chia-Lin Cheng, Chung-Hsing Wang, Hsing-Chien Huang, Yee-Wen Chen +1 more | 2004-09-07 |
| 6587997 | Automatic resistance and capacitance technology file generator for multiple RC extractors | Steven Chen | 2003-07-01 |