Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7802209 | Method for reducing timing libraries for intra-die model in statistical static timing analysis | Louis Chaochiuan Liu, Ssu-Chia Chang | 2010-09-21 |
| 7155696 | Interconnection routing method | Bih-Cherng Chen | 2006-12-26 |
| 7103862 | Method to design and verify an integrated circuit device with multiple power domains | Nai-Yin Sung, Jan-Hun Tsai | 2006-09-05 |
| 6789248 | Method and apparatus to perform resistance and capacitance (RC) parameter customization for better timing closure results in physical synthesis and optimization | Lee-Chung Lu, Cliff Hou, Chia-Lin Cheng, Chung-Hsing Wang, Yee-Wen Chen +1 more | 2004-09-07 |
| 5914892 | Structure and method of array multiplication | Shyh-Jye Wang, Chi-Chiang Wu | 1999-06-22 |
| 5867453 | Self-setup non-overlap clock generator | Shyh-Jye Wang, Chi-Chiang Wu | 1999-02-02 |