Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11585831 | Test probing structure | Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chin-Chou Liu +2 more | 2023-02-21 |
| 10861830 | Semiconductor device | Ming-Tsun Lin, Hau Tao | 2020-12-08 |
| 10782318 | Test probing structure | Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chin-Chou Liu +2 more | 2020-09-22 |
| 10535638 | Semiconductor device | Ming-Tsun Lin, Hau Tao | 2020-01-14 |
| 10262974 | Method of manufacturing a semiconductor device | Ming-Tsun Lin, Hau Tao | 2019-04-16 |
| 10002854 | Semiconductor device and method | Ming-Tsun Lin, Hau Tao | 2018-06-19 |
| 9817029 | Test probing structure | Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chin-Chou Liu +2 more | 2017-11-14 |
| 9741688 | Method for manufacturing a semiconductor device | Ming-Tsun Lin, Hau Tao | 2017-08-22 |
| 9704766 | Interposers of 3-dimensional integrated circuit package systems and methods of designing the same | Sandeep Kumar Goel, Mill-Jer Wang, Chung-Sheng Yuan, Tom C. Chen, Chin-Chou Liu +1 more | 2017-07-11 |
| 9660017 | Microelectronic package with surface mounted passive element | Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang | 2017-05-23 |
| 9646128 | System and method for validating stacked dies by comparing connections | Ashok Mehta, Stanley John, Kai-Yuan Ting, Sandeep Kumar Goel | 2017-05-09 |
| 9613174 | Common template for electronic article | William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan +2 more | 2017-04-04 |
| 9542517 | Techniques for fast resonance convergence | — | 2017-01-10 |
| 9385073 | Packages having integrated devices and methods of forming same | — | 2016-07-05 |
| 9385110 | Semiconductor device and method | Ming-Tsun Lin, Hau Tao | 2016-07-05 |
| 9190345 | Semiconductor devices and methods of manufacture thereof | Szu-Ying Chen, Tzu-Hsuan Hsu, Dun-Nian Yaung | 2015-11-17 |
| 9104835 | Systems and methods for determining effective capacitance to facilitate a timing analysis | Cheng-Hung Yeh, Chi-Ting Huang | 2015-08-11 |
| 9047432 | System and method for validating stacked dies by comparing connections | Ashok Mehta, Stanley John, Kai-Yuan Ting, Sandeep Kumar Goel | 2015-06-02 |
| 9003338 | Common template for electronic article | William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Sean Lee, Chung-Sheng Yuan +2 more | 2015-04-07 |
| 8910101 | Systems and methods for determining effective capacitance to facilitate a timing analysis | Cheng-Hung Yeh, Chi-Ting Huang | 2014-12-09 |
| 8856710 | Tool and method for modeling interposer RC couplings | Ze-Ming Wu, Meng-Lin Chung, Chih-Chia Chen, Li Ding, Sa-Lly Liu | 2014-10-07 |
| 8402404 | Stacked die interconnect validation | Ashok Mehta, Stanley John, Kai-Yuan Ting, Sandeep Kumar Goel | 2013-03-19 |
| 8269350 | Reducing the switching noise on substrate with high grounding resistance | Chih-Chia Chen, Meng-Lin Chung | 2012-09-18 |