ZW

Ze-Ming Wu

TSMC: 13 patents #2,298 of 12,232Top 20%
Overall (All Time): #364,974 of 4,157,543Top 9%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
12361199 Integrated circuit layout generation method Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more 2025-07-15
12093629 Method of manufacturing semiconductor device and system for same Ke-Ying Su, Po-Jui Lin 2024-09-17
11907636 Integrated circuit layout generation method Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more 2024-02-20
11681847 Method of manufacturing semiconductor device and system for same Ke-Ying Su, Po-Jui Lin 2023-06-20
11392749 Integrated circuit layout generation method and system Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more 2022-07-19
10846456 Integrated circuit modeling methods and systems Ke-Ying Su, Jon-Hsu Ho, Ke-Wei Su, Liang Chen, Wen-Hsing Hsieh +4 more 2020-11-24
9582630 System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction Shih-Hsin Chen, Chien-Chih Kuo, Kai-Ming Liu, Hsien-Hsin Sean Lee 2017-02-28
9021412 RC extraction methodology for floating silicon substrate with TSV Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao 2015-04-28
8904337 Semiconductor device design method, system and computer-readable medium Ching-Shun Yang, Hsiao-Chu Chao, Yi-Kan Cheng 2014-12-02
8856710 Tool and method for modeling interposer RC couplings Chao-Yang Yeh, Meng-Lin Chung, Chih-Chia Chen, Li Ding, Sa-Lly Liu 2014-10-07
8826213 Parasitic capacitance extraction for FinFETs Chia-Ming Ho, Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Hsien-Hsin Sean Lee 2014-09-02
8707245 Semiconductor device design method, system and computer-readable medium Ching-Shun Yang, Hsiao-Shu Chao, Yi-Kan Cheng 2014-04-22
8607179 RC extraction methodology for floating silicon substrate with TSV Ching-Shun Yang, Ke-Ying Su, Hsiao-Shu Chao 2013-12-10