Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10140407 | Method, device and computer program product for integrated circuit layout generation | Adari Rama Bhadra Rao, Meng-Kai Hsu, Kuang-Hung Chang, Ke-Ying Su, Wen-Hao Chen +1 more | 2018-11-27 |
| 10019548 | Method of generating modified layout and system therefor | Ke-Ying Su, Hsien-Hsin Sean Lee | 2018-07-10 |
| 9922162 | Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout | C. Y. Chen, Hsiu-Wen Hsueh, Jun Huang, Shao-Heng Chou | 2018-03-20 |
| 9710588 | Method of generating modified layout for RC extraction | Ke-Ying Su, Hsien-Hsin Sean Lee | 2017-07-18 |
| 9230052 | Method of generating a simulation model of a predefined fabrication process | Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng | 2016-01-05 |
| 9218448 | Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout | C. Y. Chen, Hsiu-Wen Hsueh, Jun Huang, Shao-Heng Chou | 2015-12-22 |
| 8954900 | Multi-patterning mask decomposition method and system | Kun Ting Tsai, Tsung-Han Wu, Ke-Ying Su, Hsien-Hsin Sean Lee | 2015-02-10 |
| 8904314 | RC extraction for multiple patterning layout design | Te-Yu Liu, Ke-Ying Su, Hsien-Hsin Sean Lee | 2014-12-02 |
| 8887106 | Method of generating a bias-adjusted layout design of a conductive feature and method of generating a simulation model of a predefined fabrication process | Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng | 2014-11-11 |
| 8887116 | Flexible pattern-oriented 3D profile for advanced process nodes | Te-Yu Liu, Austin Chingyu Chiang, Meng-Fan Wu, Ke-Ying Su | 2014-11-11 |
| 8826213 | Parasitic capacitance extraction for FinFETs | Ke-Ying Su, Hsiao-Shu Chao, Yi-Kan Cheng, Ze-Ming Wu, Hsien-Hsin Sean Lee | 2014-09-02 |
| 8572537 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Gwan Sin Chang, Chien-Wen Chen | 2013-10-29 |
| 8214784 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Gwan Sin Chang, Chien-Wen Chen | 2012-07-03 |
| 7818698 | Accurate parasitic capacitance extraction for ultra large scale integrated circuits | Ke-Ying Su, Gwan Sin Chang, Chien-Wen Chen | 2010-10-19 |
| 7181664 | Method on scan chain reordering for lowering VLSI power consumption | Herng-Jer Lee, Chia-Chi Chu, Wu-Shiung Feng | 2007-02-20 |
| 6845582 | Photo-frame style photo album | Shv-Chen Ho | 2005-01-25 |