Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417955 | Thermal sensor device by back end of line metal resistor | Yu-Hsiang Chen, Szu-Lin Liu, Wen-Sheh Huang, Chloe Chen, Wei-Lin Lai | 2025-09-16 |
| 12387977 | Self-aligned scheme for semiconductor device and method of forming the same | Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang | 2025-08-12 |
| 12368103 | Diffusion barrier layer for conductive via to decrease contact resistance | Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng | 2025-07-22 |
| 12362235 | Barrier free interface between BEOL interconnects | Chii-Ping Chen, Po-Hsiang Huang, Ya-Ching Tseng | 2025-07-15 |
| 12347770 | One-time-programmable device structure | Yu-Hsiang Chen, Wen-Sheh Huang, Po-Hsiang Huang | 2025-07-01 |
| 12341101 | Method for forming a semiconductor structure by diffusing manganese from a seed layer to a barrier layer | Cai-Ling Wu, Chii-Ping Chen, Po-Hsiang Huang, Chi-Feng Lin | 2025-06-24 |
| 12243816 | Semiconductor structure havbing an enhanced E-fuse and a method making the same | An-Jiao Fu, Po-Hsiang Huang, Derek Hsen Dai Hsu, Meng-Sheng Chang | 2025-03-04 |
| 12119262 | Semiconductor device structure with resistive element | Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen | 2024-10-15 |
| 12040178 | Method for manufacturing semiconductor structure with resistive elements | Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen | 2024-07-16 |
| 11901228 | Self-aligned scheme for semiconductor device and method of forming the same | Cai-Ling Wu, Wei-Ren Wang, Po-Hsiang Huang, Chii-Ping Chen, Jen Hung Wang | 2024-02-13 |
| 11830770 | Self-aligned scheme for semiconductor device and method of forming the same | Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang | 2023-11-28 |
| 11798848 | Semiconductor device structure with resistive element | Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen | 2023-10-24 |
| 11742291 | Diffusion barrier layer for conductive via to decrease contact resistance | Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng | 2023-08-29 |
| 11694926 | Barrier free interface between beol interconnects | Chii-Ping Chen, Po-Hsiang Huang, Ya-Ching Tseng | 2023-07-04 |
| 11670501 | Semiconductor device structure with resistive elements | Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen | 2023-06-06 |
| 11551968 | Inter-wire cavity for low capacitance | Jiing-Feng Yang, Chii-Ping Chen, Po-Hsiang Huang, Chang-Wen Chen, Cai-Ling Wu | 2023-01-10 |
| 11410926 | E-fuse enhancement by underlayer layout design | An-Jiao Fu, Po-Hsiang Huang, Derek Hsen Dai Hsu, Meng-Sheng Chang | 2022-08-09 |
| 11362035 | Diffusion barrier layer for conductive via to decrease contact resistance | Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng | 2022-06-14 |
| 11342222 | Self-aligned scheme for semiconductor device and method of forming the same | Cai-Ling Wu, Ya-Ching Tseng, Chii-Ping Chen, Neng-Jye Yang | 2022-05-24 |
| 11217482 | Method for forming semiconductor device with resistive element | Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen | 2022-01-04 |
| 10985011 | Structure and formation method of semiconductor device with resistive elements | Yu-Hsiang Chen, Wen-Sheh Huang, Chii-Ping Chen, Wan-Te Chen | 2021-04-20 |
| 10515852 | Structure and formation method of semiconductor device with resistive element | Wen-Sheh Huang, Yu-Hsiang Chen, Chii-Ping Chen | 2019-12-24 |
| 9922162 | Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout | Chia-Ming Ho, C. Y. Chen, Jun Huang, Shao-Heng Chou | 2018-03-20 |
| 9218448 | Resistive capacitance determination method for multiple-patterning-multiple spacer integrated circuit layout | Chia-Ming Ho, C. Y. Chen, Jun Huang, Shao-Heng Chou | 2015-12-22 |