Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12322742 | Semiconductor structure and manufacturing method thereof | Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng +4 more | 2025-06-03 |
| 12253558 | Circuit test structure and method of using | Ching-Fang Chen, Chih-Hsien Lin | 2025-03-18 |
| 12125810 | Delamination sensor | Chih-Hsuan Tai, Ming-Chung Wu, Kuo-Wen Chen | 2024-10-22 |
| 11855066 | Semiconductor structure and manufacturing method thereof | Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng +4 more | 2023-12-26 |
| 11828790 | Circuit test structure and method of using | Ching-Fang Chen, Chih-Hsien Lin | 2023-11-28 |
| 11616029 | Delamination sensor | Chih-Hsuan Tai, Ming-Chung Wu, Kuo-Wen Chen | 2023-03-28 |
| 11335672 | Semiconductor structure and manufacturing method thereof | Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng +4 more | 2022-05-17 |
| 11002788 | Circuit test structure | Ching-Fang Chen, Chih-Hsien Lin | 2021-05-11 |
| 10879162 | Integrated fan-out packages | Shin-Puu Jeng, Dai-Jang Chen, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung +1 more | 2020-12-29 |
| 10741537 | Semiconductor structure and manufacturing method thereof | Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng +4 more | 2020-08-11 |
| 10347574 | Integrated fan-out packages | Shin-Puu Jeng, Dai-Jang Chen, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung +1 more | 2019-07-09 |
| 10288676 | Circuit test structure | Ching-Fang Chen, Chih-Hsien Lin | 2019-05-14 |
| 10269586 | Package structure and methods of forming same | Bruce C. S. Chou, Chih-Hsien Lin, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin +1 more | 2019-04-23 |
| 9941239 | Electrostatic discharge protection apparatus and process | Wen-Chien Chang, Dai-Jang Chen, Chih-Hsien Lin | 2018-04-10 |
| 9689914 | Method of testing a three-dimensional integrated circuit | Ching-Fang Chen, Chih-Hsien Lin | 2017-06-27 |
| 9607999 | System and method of UV programming of non-volatile semiconductor memory | Chih-Hsien Lin | 2017-03-28 |
| 9491840 | Electrostatic discharge protection apparatus and process | Wen-Chien Chang, Dai-Jang Chen, Chih-Hsien Lin | 2016-11-08 |
| 9209048 | Two step molding grinding for packaging applications | Wen-Chun Huang, Chien-Chen Li, Kuo-Chio Liu, Ruey-Yun Shiue, Hsi-Kuei Cheng +3 more | 2015-12-08 |
| 9190148 | System and method of UV programming of non-volatile semiconductor memory | Chih-Hsien Lin | 2015-11-17 |
| 9159564 | Method of shielding through silicon vias in a passive interposer | Chih-Hsien Lin, Meng-Lin Chung | 2015-10-13 |
| 9040986 | Three dimensional integrated circuit having a resistance measurement structure and method of use | Ching-Fang Chen, Chih-Hsien Lin | 2015-05-26 |
| 8970023 | Package structure and methods of forming same | Bruce C. S. Chou, Chih-Hsien Lin, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin +1 more | 2015-03-03 |
| 8664540 | Interposer testing using dummy connections | Chih-Hsien Lin, Wei-Sho Hung | 2014-03-04 |
| 8618640 | Method of shielding through silicon vias in a passive interposer | Chih-Hsien Lin, Meng-Lin Chung | 2013-12-31 |
| 7462906 | Flash memory process with high voltage LDMOS embedded | Cheng-Hsiung Kuo, Chin-Huang Wang | 2008-12-09 |