Issued Patents All Time
Showing 1–25 of 141 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381180 | Multi-chip packages and methods of forming the same | Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Shin-Puu Jeng, Hsiao-Wen Lee | 2025-08-05 |
| 12382587 | Methods and systems for improving surface mount joinder | Shih-Ting Hung, Jyun-Lin Wu, Yao-Chun Chuang, Yinlung Lu | 2025-08-05 |
| 12334654 | Network communication device with antenna frame | Chih-Wen Tseng | 2025-06-17 |
| 12205853 | Integrated circuit test method and structure thereof | Hsien-Wei Chen | 2025-01-21 |
| 12198996 | Integrated fan-out package, package-on-package structure, and manufacturing method thereof | Shin-Puu Jeng, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang, Po-Yao Chuang | 2025-01-14 |
| 12113025 | Semiconductor package with dual sides of metal routing | Shin-Puu Jeng, Shuo-Mao Chen, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin | 2024-10-08 |
| 12009316 | Semiconductor structure and method of manufacturing a semiconductor structure | Hsien-Wei Chen, Jie Chen | 2024-06-11 |
| 11798898 | Package structure | Hsiao-Wen Lee, Shin-Puu Jeng | 2023-10-24 |
| 11756928 | Multi-chip packages | Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Shin-Puu Jeng, Hsiao-Wen Lee | 2023-09-12 |
| 11688728 | Integrated circuit structure and method for reducing polymer layer delamination | Jing-Cheng Lin, Jui-Pin Hung, Min-Chen Lin | 2023-06-27 |
| 11532524 | Integrated circuit test method and structure thereof | Hsien-Wei Chen | 2022-12-20 |
| 11456257 | Semiconductor package with dual sides of metal routing | Shin-Puu Jeng, Shuo-Mao Chen, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin | 2022-09-27 |
| 11430739 | Structure and formation method of package structure with fan-out structure | Po-Hao Tsai, Shin-Puu Jeng, Meng-Liang Lin, Shih-Yung PENG, Shih-Ting Hung | 2022-08-30 |
| 11342306 | Multi-chip wafer level packages | Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Shin-Puu Jeng, Hsiao-Wen Lee | 2022-05-24 |
| 11329031 | Structure and formation method for chip package | Jui-Pin Hung, Cheng-Lin Huang, Shin-Puu Jeng | 2022-05-10 |
| 11189596 | Methods of forming multi-chip wafer level packages | Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Shin-Puu Jeng, Hsiao-Wen Lee | 2021-11-30 |
| 11114313 | Wafer level mold chase | Po-Hao Tsai, Yi-Wen Wu, Shin-Puu Jeng | 2021-09-07 |
| 11081475 | Integrated circuit structure and method for reducing polymer layer delamination | Jing-Cheng Lin, Jui-Pin Hung, Min-Chen Lin | 2021-08-03 |
| 11075132 | Integrated fan-out package, package-on-package structure, and manufacturing method thereof | Shin-Puu Jeng, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang, Po-Yao Chuang | 2021-07-27 |
| 11056445 | Package structure with buffer layer sandwiched between encapsulation layer and semiconductor substrate | Hsiao-Wen Lee, Shin-Puu Jeng | 2021-07-06 |
| 10879162 | Integrated fan-out packages | Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Chih-Hsien Lin, Shih-Ting Hung +1 more | 2020-12-29 |
| 10867924 | Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing | Shin-Puu Jeng, Shuo-Mao Chen, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin | 2020-12-15 |
| 10861801 | Wafer level package (WLP) and method for forming the same | Shin-Puu Jeng | 2020-12-08 |
| 10763239 | Multi-chip wafer level packages and methods of forming the same | Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Shin-Puu Jeng, Hsiao-Wen Lee | 2020-09-01 |
| 10748882 | Structure and formation method for chip package | Jui-Pin Hung, Cheng-Lin Huang, Shin-Puu Jeng | 2020-08-18 |