Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368109 | Interposer structure for semiconductor package including peripheral metal pad around alignment mark and methods of fabricating same | Hsien-Wei Chen, Shin-Puu Jeng | 2025-07-22 |
| 12354938 | Semiconductor package and methods of manufacturing | Hsien-Wei Chen, Shin-Puu Jeng | 2025-07-08 |
| 12354989 | Package structure with conductive via structure | Po-Yao Chuang, Shin-Puu Jeng | 2025-07-08 |
| 12308321 | Structures to increase substrate routing density and methods of forming the same | Hsien-Wei Chen, Shin-Puu Jeng | 2025-05-20 |
| 12308322 | Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same | Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2025-05-20 |
| 12300592 | Fan-out package with controllable standoff | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2025-05-13 |
| 12205861 | Manufacturing method of semiconductor package including forming cavity in circuit substrate without exposing floor plate | Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng | 2025-01-21 |
| 12199084 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou | 2025-01-14 |
| 12176337 | Semiconductor devices and methods of manufacturing | Yi-Wen Wu, Po-Yao Chuang, Techi Wong, Shih-Ting Hung, Po-Hao Tsai +1 more | 2024-12-24 |
| 12165980 | Semiconductor package and methods of manufacturing | Hsien-Wei Chen, Shin-Puu Jeng | 2024-12-10 |
| 12094819 | Method for forming package structure | Po-Hao Tsai, Techi Wong, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2024-09-17 |
| 12074104 | Integrated circuit packages with ring-shaped substrates | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2024-08-27 |
| 12057424 | Package structure and method for forming the same | Po-Yao Chuang, Shin-Puu Jeng | 2024-08-06 |
| 11948892 | Formation method of chip package with fan-out feature | Po-Hao Tsai, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng | 2024-04-02 |
| 11908764 | Semiconductor package including a circuit substrate having a cavity and a floor plate embedded in a dielectric material and a semiconductor die disposed in the cavity | Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng | 2024-02-20 |
| 11901279 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang | 2024-02-13 |
| 11901277 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang | 2024-02-13 |
| 11854955 | Fan-out package with controllable standoff | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2023-12-26 |
| 11855059 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou | 2023-12-26 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2023-11-21 |
| 11682599 | Chip package structure with molding layer and method for forming the same | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2023-06-20 |
| 11637054 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Shin-Puu Jeng, Yi-Wen Wu, Po-Yao Chuang | 2023-04-25 |
| 11527474 | Integrated circuit package and method | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2022-12-13 |
| 11430739 | Structure and formation method of package structure with fan-out structure | Po-Hao Tsai, Hsien-Wen Liu, Shin-Puu Jeng, Shih-Yung PENG, Shih-Ting Hung | 2022-08-30 |
| 11430776 | Semiconductor devices and methods of manufacturing | Yi-Wen Wu, Po-Yao Chuang, Techi Wong, Shih-Ting Hung, Po-Hao Tsai +1 more | 2022-08-30 |