Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11380666 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou | 2022-07-05 |
| 11362010 | Structure and formation method of chip package with fan-out feature | Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Techi Wong, Shin-Puu Jeng | 2022-06-14 |
| 11322447 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Yi-Wen Wu, Shin-Puu Jeng, Techi Wong | 2022-05-03 |
| 11239173 | Structure and formation method of chip package with fan-out feature | Po-Hao Tsai, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng | 2022-02-01 |
| 11164754 | Fan-out packages and methods of forming the same | Po-Hao Tsai, Ming-Chih Yew, Chia-Kuei Hsu, Shin-Puu Jeng, Po-Yao Chuang +2 more | 2021-11-02 |
| 11101214 | Package structure with dam structure and method for forming the same | Po-Hao Tsai, Techi Wong, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2021-08-24 |
| 11075151 | Fan-out package with controllable standoff | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2021-07-27 |
| 10804254 | Fan-out package with cavity substrate | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou | 2020-10-13 |
| 10790162 | Integrated circuit package and method | Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Po-Yao Chuang, Shin-Puu Jeng | 2020-09-29 |
| 10446522 | Methods of forming multiple conductive features in semiconductor devices in a same formation process | Cheng-Lin Huang | 2019-10-15 |
| 9343419 | Bump structures for semiconductor package | Chen-Hua Yu, Jy-Jie Gau, Cheng-Lin Huang, Jing-Cheng Lin, Kuo-Ching Hsu | 2016-05-17 |