Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308322 | Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng | 2025-05-20 |
| 12308313 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2025-05-20 |
| 12300592 | Fan-out package with controllable standoff | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2025-05-13 |
| 12237262 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2025-02-25 |
| 12199084 | Fan-out package with cavity substrate | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2025-01-14 |
| 12176337 | Semiconductor devices and methods of manufacturing | Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Shih-Ting Hung, Po-Hao Tsai +1 more | 2024-12-24 |
| 12170274 | Semiconductor packages and methods of forming same | Shin-Puu Jeng, Po-Yao Chuang, Shuo-Mao Chen, Meng-Wei Chou | 2024-12-17 |
| 12131984 | Heterogeneous fan-out structure and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng | 2024-10-29 |
| 12100666 | Method for forming chip package structure | Shin-Puu Jeng, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Chuang | 2024-09-24 |
| 12094819 | Method for forming package structure | Po-Hao Tsai, Meng-Liang Lin, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2024-09-17 |
| 12074104 | Integrated circuit packages with ring-shaped substrates | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2024-08-27 |
| 12046548 | Chip package with redistribution structure having multiple chips | Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen | 2024-07-23 |
| 11948892 | Formation method of chip package with fan-out feature | Po-Hao Tsai, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2024-04-02 |
| 11855059 | Fan-out package with cavity substrate | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin | 2023-12-26 |
| 11854955 | Fan-out package with controllable standoff | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-12-26 |
| 11848265 | Semiconductor package with improved interposer structure | Yi-Wen Wu, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2023-12-19 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Yi-Wen Wu, Shin-Puu Jeng | 2023-11-21 |
| 11764159 | Package with fan-out structures | Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang | 2023-09-19 |
| 11682599 | Chip package structure with molding layer and method for forming the same | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2023-06-20 |
| 11670577 | Chip package with redistribution structure having multiple chips | Shin-Puu Jeng, Po-Hao Tsai, Po-Yao Chuang, Feng-Cheng Hsu, Shuo-Mao Chen | 2023-06-06 |
| 11646256 | Heterogeneous fan-out structure and method of manufacture | Po-Hao Tsai, Po-Yao Chuang, Shin-Puu Jeng | 2023-05-09 |
| 11600575 | Method for forming chip package structure | Shin-Puu Jeng, Po-Yao Lin, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Chuang | 2023-03-07 |
| 11600573 | Structure and formation method of chip package with conductive support elements to reduce warpage | Po-Hao Tsai, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng | 2023-03-07 |
| 11527474 | Integrated circuit package and method | Po-Hao Tsai, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2022-12-13 |
| 11430776 | Semiconductor devices and methods of manufacturing | Yi-Wen Wu, Po-Yao Chuang, Meng-Liang Lin, Shih-Ting Hung, Po-Hao Tsai +1 more | 2022-08-30 |