Issued Patents All Time
Showing 1–25 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412857 | Hybrid micro-bump integration with redistribution layer | Ting-Li Yang, Po-Hao Tsai, Sheng-Pin Yang, Hao-Chun Liu | 2025-09-09 |
| 12388028 | Package structure | Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang | 2025-08-12 |
| 12308322 | Dual-sided routing in 3D semiconductor system-in-package structure and methods of forming the same | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Shin-Puu Jeng, Techi Wong | 2025-05-20 |
| 12308313 | Semiconductor package with improved interposer structure | Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2025-05-20 |
| 12300598 | Package structure and method of fabricating the same | Hung-Jui Kuo, Ming-Che Ho | 2025-05-13 |
| 12237262 | Semiconductor package with improved interposer structure | Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2025-02-25 |
| 12176337 | Semiconductor devices and methods of manufacturing | Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai +1 more | 2024-12-24 |
| 12094819 | Method for forming package structure | Po-Hao Tsai, Techi Wong, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng | 2024-09-17 |
| 12051654 | Package structure and method of fabricating the same | Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang | 2024-07-30 |
| 11901279 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Po-Yao Chuang | 2024-02-13 |
| 11901277 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Po-Yao Chuang | 2024-02-13 |
| 11855028 | Hybrid micro-bump integration with redistribution layer | Ting-Li Yang, Po-Hao Tsai, Sheng-Pin Yang, Hao-Chun Liu | 2023-12-26 |
| 11855014 | Semiconductor device and method | Chen-Hua Yu, Ming-Che Ho, Hung-Jui Kuo, Tzung-Hui Lee | 2023-12-26 |
| 11848265 | Semiconductor package with improved interposer structure | Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng | 2023-12-19 |
| 11824007 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Shin-Puu Jeng, Techi Wong | 2023-11-21 |
| 11804451 | Package structure and method of fabricating the same | Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang | 2023-10-31 |
| 11637054 | Semiconductor package and method of manufacturing the same | Shih-Ting Hung, Meng-Liang Lin, Shin-Puu Jeng, Po-Yao Chuang | 2023-04-25 |
| 11600573 | Structure and formation method of chip package with conductive support elements to reduce warpage | Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng | 2023-03-07 |
| 11594484 | Forming bonding structures by using template layer as templates | Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky +3 more | 2023-02-28 |
| 11430776 | Semiconductor devices and methods of manufacturing | Po-Yao Chuang, Meng-Liang Lin, Techi Wong, Shih-Ting Hung, Po-Hao Tsai +1 more | 2022-08-30 |
| 11410953 | Via structure for packaging and a method of forming | Ming-Che Ho, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu | 2022-08-09 |
| 11362010 | Structure and formation method of chip package with fan-out feature | Meng-Liang Lin, Po-Hao Tsai, Po-Yao Chuang, Techi Wong, Shin-Puu Jeng | 2022-06-14 |
| 11322447 | Dual-sided routing in 3D SiP structure | Po-Hao Tsai, Po-Yao Chuang, Meng-Liang Lin, Shin-Puu Jeng, Techi Wong | 2022-05-03 |
| 11302650 | Package structure and method of fabricating the same | Shin-Puu Jeng, Shih-Ting Hung, Po-Yao Chuang | 2022-04-12 |
| 11257714 | Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same | Chien Ling Hwang, Chun-Chieh Wang, Chung-Shi Liu | 2022-02-22 |