AC

Anshuman Chandra

SY Synopsys: 6 patents #194 of 2,302Top 9%
TSMC: 1 patents #8,466 of 12,232Top 70%
Overall (All Time): #697,387 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12066490 Wrapper cell design and built-in self-test architecture for 3DIC test and diagnosis Sandeep Kumar Goel 2024-08-20
10621298 Automatically generated schematics and visualization Subramanian Chebiyam, Rohit Kapur 2020-04-14
10067187 Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment Subramanian Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur 2018-09-04
9417287 Scheme for masking output of scan chains in test circuit Subramanian Chebiyam, Jyotirmoy Saikia, Parthajit Bhattacharya, Rohit Kapur 2016-08-16
9239897 Hierarchical testing architecture using core circuit with pseudo-interfaces Subramanian Chebiyam, Santosh Kulkarni, Rohit Kapur 2016-01-19
8479067 Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry Jyotirmoy Saikia, Rohit Kapur 2013-07-02
8065651 Implementing hierarchical design-for-test logic for modular circuit design Rohit Kapur, Yasunari Kanzawa, Jyotirmoy Saikia 2011-11-22