| 10605863 |
Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits |
Subhadip Kundu, Rohit Kapur |
2020-03-31 |
| 10067187 |
Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment |
Anshuman Chandra, Subramanian Chebiyam, Jyotirmoy Saikia, Rohit Kapur |
2018-09-04 |
| 9568550 |
Identifying failure indicating scan test cells of a circuit-under-test |
Subhadip Kundu, Rohit Kapur |
2017-02-14 |
| 9417287 |
Scheme for masking output of scan chains in test circuit |
Anshuman Chandra, Subramanian Chebiyam, Jyotirmoy Saikia, Rohit Kapur |
2016-08-16 |
| 9411014 |
Reordering or removal of test patterns for detecting faults in integrated circuit |
Sushovan Podder, Rohit Kapur |
2016-08-09 |
| 9329235 |
Localizing fault flop in circuit by using modified test pattern |
Rohit Kapur |
2016-05-03 |
| 8521464 |
Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization |
Ashwin Kumar, Ramakrishnan Balasubramanian, Rohit Kapur, Rajesh Uppuluri, Jyotirmoy Saikia +1 more |
2013-08-27 |