Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10203370 | Scheme for masking output of scan chains in test circuit | Rohit Kapur | 2019-02-12 |
| 10067187 | Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment | Anshuman Chandra, Subramanian Chebiyam, Parthajit Bhattacharya, Rohit Kapur | 2018-09-04 |
| 9588179 | Scheme for masking output of scan chains in test circuit | Rohit Kapur | 2017-03-07 |
| 9417287 | Scheme for masking output of scan chains in test circuit | Anshuman Chandra, Subramanian Chebiyam, Parthajit Bhattacharya, Rohit Kapur | 2016-08-16 |
| 8954918 | Test design optimizer for configurable scan architectures | Rohit Kapur, Rajesh Uppuluri, Pramod Notiyath, Tammy Fernandes, Santosh Kulkarni +1 more | 2015-02-10 |
| 8584073 | Test design optimizer for configurable scan architectures | Rohit Kapur, Rajesh Uppuluri, Pramod Notiyath, Tammy Fernandes, Santosh Kulkarni +1 more | 2013-11-12 |
| 8521464 | Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization | Ashwin Kumar, Ramakrishnan Balasubramanian, Rohit Kapur, Rajesh Uppuluri, Parthajit Bhattacharya +1 more | 2013-08-27 |
| 8479067 | Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry | Anshuman Chandra, Rohit Kapur | 2013-07-02 |
| 8065651 | Implementing hierarchical design-for-test logic for modular circuit design | Rohit Kapur, Anshuman Chandra, Yasunari Kanzawa | 2011-11-22 |