Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400725 | Conducting built-in self-test of memory macro | Saman M. I. Adham, Vineet Joshi, Ted Wong | 2025-08-26 |
| 12385973 | Scan architecture for interconnect testing in 3D integrated circuits | Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham | 2025-08-12 |
| 12033710 | System and method for conducting built-in self-test of memory macro | Ted Wong, Saman M. I. Adham | 2024-07-09 |
| 11899064 | Scan architecture for interconnect testing in 3D integrated circuits | Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham | 2024-02-13 |
| 11823758 | Conducting built-in self-test of memory macro | Saman M. I. Adham, Ted Wong, Vineet Joshi | 2023-11-21 |
| 11549984 | Scan architecture for interconnect testing in 3D integrated circuits | Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham | 2023-01-10 |
| 10539617 | Scan architecture for interconnect testing in 3D integrated circuits | Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham | 2020-01-21 |