Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6212542 | Method and system for executing a program within a multiscalar processor by processing linked thread descriptors | James Allan Kahle, Robert G. McDonald, Edward L. Swarthout | 2001-04-03 |
| 6061777 | Apparatus and method for reducing the number of rename registers required in the operation of a processor | Hoichi Cheong, Paul J. Jordan, Hung Q. Le | 2000-05-09 |
| 5995743 | Method and system for interrupt handling during emulation in a data processing system | James Allan Kahle | 1999-11-30 |
| 5961639 | Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution | Robert G. McDonald, Edward L. Swarthout | 1999-10-05 |
| 5956495 | Method and system for processing branch instructions during emulation in a data processing system | James Allan Kahle | 1999-09-21 |
| 5953520 | Address translation buffer for data processing system emulation mode | — | 1999-09-14 |
| 5913925 | Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order | James Allan Kahle, Robert G. McDonald | 1999-06-22 |
| 5913054 | Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle | Rajesh B. Patel, Albert J. Loper, Romesh Mangho Jessani | 1999-06-15 |
| 5897654 | Method and system for efficiently fetching from cache during a cache fill operation | Lee Evan Eisen, Belliappa Kuttanna, Rajesh Patel | 1999-04-27 |
| 5897655 | System and method for cache replacement within a cache set based on valid, modified or least recently used status in order of preference | — | 1999-04-27 |
| 5897666 | Generation of unique address alias for memory disambiguation buffer to avoid false collisions | Robert G. McDonald | 1999-04-27 |
| 5898864 | Method and system for executing a context-altering instruction without performing a context-synchronization operation within high-performance processors | Robert T. Golla, James Allan Kahle, Albert J. Loper | 1999-04-27 |
| 5887166 | Method and system for constructing a program including a navigation instruction | Robert G. McDonald, Edward L. Swarthout | 1999-03-23 |
| 5872948 | Processor and method for out-of-order execution of instructions based upon an instruction parameter | Rajesh B. Patel, Romesh Mangho Jessani, Michael Putrino | 1999-02-16 |
| 5870616 | System and method for reducing power consumption in an electronic circuit | Albert J. Loper | 1999-02-09 |
| 5870577 | System and method for dispatching two instructions to the same execution unit in a single cycle | Rajesh B. Patel, Romesh Mangho Jessani | 1999-02-09 |
| 5870575 | Indirect unconditional branches in data processing system emulation mode | James Allan Kahle | 1999-02-09 |
| 5867684 | Method and processor that permit concurrent execution of a store multiple instruction and a dependent instruction | James Allan Kahle, Albert J. Loper, Aubrey Deene Ogden | 1999-02-02 |
| 5850563 | Processor and method for out-of-order completion of floating-point operations during load/store multiple operations | Albert J. Loper | 1998-12-15 |
| 5812823 | Method and system for performing an emulation context save and restore that is transparent to the operating system | James Allan Kahle, Arturo Martin-de-Nicolas | 1998-09-22 |
| 5812812 | Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue | Muhammad Afsar, Romesh Mangho Jessani, Robert G. McDonald, Mukesh Sharma | 1998-09-22 |
| 5809323 | Method and apparatus for executing fixed-point instructions within idle execution units of a superscalar processor | Lee Evan Eisen, Robert T. Golla, Sung Ho Park, Rajesh B. Patel, Michael Putrino | 1998-09-15 |
| 5805916 | Method and apparatus for dynamic allocation of registers for intermediate floating-point results | Michael Putrino, Romesh Mangho Jessani | 1998-09-08 |
| 5805907 | System and method for reducing power consumption in an electronic circuit | Albert J. Loper | 1998-09-08 |
| 5802572 | Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache | Rajesh Patel | 1998-09-01 |