Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405890 | Method and apparatus for leveraging simultaneous multithreading for bulk compute operations | Anant Vithal Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer +2 more | 2025-09-02 |
| 12112171 | Loop support extensions | Anant Vithal Nori, Shankar Balachandran, Sreenivas Subramoney, Joydeep Rakshit, Vedvyas Shanbhogue +1 more | 2024-10-08 |
| 11347828 | Methods, apparatus, articles of manufacture to perform accelerated matrix multiplication | Biji George, Om Ji Omer, Dipan Kumar Mandal, Cormac Brick, Lance Hacking +1 more | 2022-05-31 |
| 10181171 | Sharing resources between a CPU and GPU | Eric Sprangle, Matt Craighead, Chris Goodman | 2019-01-15 |
| 9600283 | Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode | Ethan Schuchman, Hong Wang, Chris Weaver, Asit K. Mallick, Vivek K. De +1 more | 2017-03-21 |
| 9164764 | Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode | Ethan Schuchman, Hong Wang, Chris Weaver, Asit K. Mallick, Vivek K. De +1 more | 2015-10-20 |
| 8762692 | Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode | Ethan Schuchman, Hong Wang, Chris Weaver, Asit K. Mallick, Vivek K. De +1 more | 2014-06-24 |
| 8719612 | Method, system and apparatus for low-power storage of processor context information | Bruce L. Fleming, Ashish V. Choubal, Sanjoy K. Mondal | 2014-05-06 |
| 8669990 | Sharing resources between a CPU and GPU | Eric Sprangle, Matthew J. Craighead, Chris Goodman | 2014-03-11 |
| 8392728 | Reducing idle leakage power in an IC | Lance Hacking, Rajesh Patel, Ashish V. Choubal, Terry Fletcher, Steven S. Varnum +1 more | 2013-03-05 |
| 8352770 | Method, system and apparatus for low-power storage of processor context information | Bruce L. Fleming, Ashish V. Choubal, Sanjoy K. Mondal | 2013-01-08 |
| 8289850 | Interconnect bandwidth throttler | Lance Hacking, Ramana Rachakonda, Rajesh Patel | 2012-10-16 |
| 8050177 | Interconnect bandwidth throttler | Lance Hacking, Ramana Rachakonda, Rajesh Patel | 2011-11-01 |
| 7877619 | Power mode control method and circuitry | Ramana Rachakonda, Blaise Fanning, Anil K. Sabbavarapu, Rajesh Patel, Kenneth D. Shoemaker +3 more | 2011-01-25 |
| 7451295 | Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues | Robert Milstrey, Stanley J. Domen, Glenn J. Hinton | 2008-11-11 |
| 7269711 | Methods and apparatus for address generation in processors | Rajesh Patel, Robert L. Farrell, James E. Phillips, Scott E. Siers, T. W. Griffith, Jr. | 2007-09-11 |
| 7111153 | Early data return indication mechanism | Robert Milstrey, Stanley J. Domen, Glenn J. Hinton | 2006-09-19 |
| 6526485 | Apparatus and method for bad address handling | Anuradha N. Moudgal | 2003-02-25 |
| 6484240 | Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols | Robert E. Cypher, Ricky C. Hetherington | 2002-11-19 |
| 6470435 | Dual state rename recovery using register usage | Nicholas Samra, Jacob Doweck | 2002-10-22 |
| 6389517 | Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filtered | Anuradha N. Moudgal, Allan Tzeng | 2002-05-14 |
| 6347360 | Apparatus and method for preventing cache data eviction during an atomic operation | Anuradha N. Moudgal, Allan Tzeng | 2002-02-12 |
| 6321303 | Dynamically modifying queued transactions in a cache memory system | Thomas Hoy, Rajesh Patel, Michael D. Snyder | 2001-11-20 |
| 6311254 | Multiple store miss handling in a cache memory memory system | Rajesh Patel, Michael D. Snyder | 2001-10-30 |
| 6286082 | Apparatus and method to prevent overwriting of modified cache entries prior to write back | Anuradha N. Moudgal | 2001-09-04 |