Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6269427 | Multiple load miss handling in a cache memory system | Rajesh Patel, Michael D. Snyder | 2001-07-31 |
| 6073212 | Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags | Norman M. Hayes, Krishna M. Thatipelli, Ricky C. Hetherington, Fong Pong | 2000-06-06 |
| 6029006 | Data processor with circuit for regulating instruction throughput while powered and method of operation | Michael C. Alexander | 2000-02-22 |
| 5974505 | Method and system for reducing power consumption of a non-blocking cache within a data processing system | Rajesh Patel | 1999-10-26 |
| 5909697 | Reducing cache misses by snarfing writebacks in non-inclusive memory systems | Norman M. Hayes, Ricky C. Hetherington, Fong Pong, Krishna M. Thatipelli | 1999-06-01 |
| 5897654 | Method and system for efficiently fetching from cache during a cache fill operation | Lee Evan Eisen, Soummya Mallick, Rajesh Patel | 1999-04-27 |
| 5873123 | Processor and method for translating a nonphysical address into a physical address utilizing a selectively nonsequential search of page table entries | Rajesh Patel, Gunendran Thuraisingham | 1999-02-16 |
| 5787479 | Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation | Romesh Mangho Jessani, Soummya Mallick, Rajesh Patel | 1998-07-28 |
| 5737751 | Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system | Rajesh Patel, Sung Ho Park, Romesh Mangho Jessani | 1998-04-07 |
| 5721867 | Method and apparatus for executing single beat write store instructions during a cache store linefill operation | Sung Ho Park, Rajesh Patel | 1998-02-24 |