Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7739469 | Patching ROM code | Antonio Torrini, Robert Koelling, David Baker | 2010-06-15 |
| 5913054 | Method and system for processing a multiple-register instruction that permit multiple data words to be written in a single processor cycle | Soummya Mallick, Rajesh B. Patel, Albert J. Loper | 1999-06-15 |
| 5872948 | Processor and method for out-of-order execution of instructions based upon an instruction parameter | Soummya Mallick, Rajesh B. Patel, Michael Putrino | 1999-02-16 |
| 5870577 | System and method for dispatching two instructions to the same execution unit in a single cycle | Rajesh B. Patel, Soummya Mallick | 1999-02-09 |
| 5812812 | Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue | Muhammad Afsar, Soummya Mallick, Robert G. McDonald, Mukesh Sharma | 1998-09-22 |
| 5805916 | Method and apparatus for dynamic allocation of registers for intermediate floating-point results | Soummya Mallick, Michael Putrino | 1998-09-08 |
| 5787479 | Method and system for preventing information corruption in a cache memory caused by an occurrence of a bus error during a linefill operation | Belliappa Kuttanna, Soummya Mallick, Rajesh Patel | 1998-07-28 |
| 5764940 | Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruction fetch | Soummya Mallick, Rajesh Patel | 1998-06-09 |
| 5737751 | Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system | Rajesh Patel, Sung Ho Park, Belliappa Kuttanna | 1998-04-07 |
| 5737749 | Method and system for dynamically sharing cache capacity in a microprocessor | Rajesh Patel, Belliappa Kuttana | 1998-04-07 |