Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12410785 | Equalizer bearing assembly having wedged retainers | Darius J. Yakimchuk | 2025-09-09 |
| 12345250 | Lightweight, lattice structure horsehead for reciprocating pump unit | Darius J. Yakimchuk, Brent W. Pickens | 2025-07-01 |
| 11327791 | Apparatus and method for operating an issue queue | Michael Achenbach, Nicholas Andrew PFISTER, Kelvin D. Goveas, Michael Filippo, . ABHISHEK RAJA +1 more | 2022-05-10 |
| 11174856 | Apparatus and methods for counterbalancing a pumping unit | Clark E. Robison, Jeffrey J. Lembcke, Ross E. MOFFETT, Bryan A. Paulet, Phillip Andrew Briggs +2 more | 2021-11-16 |
| 11098708 | Hydraulic pumping system with piston displacement sensing and control | Kenneth J. Schmitt, Clark E. Robison, James S. Trapani, Benson Thomas | 2021-08-24 |
| 10310862 | Data processing | Michael Filippo, Glen Andrew Harris | 2019-06-04 |
| 10215012 | Apparatus and method of monitoring a rod pumping unit | Ross E. MOFFETT, Jeffrey J. Lembcke, Clark E. Robison | 2019-02-26 |
| 6535973 | Method and system for speculatively issuing instructions | Hoichi Cheong, Maureen A. Delaney, Hung Q. Le, Dung Q. Nguyen, David Wayne Victor | 2003-03-18 |
| 6484251 | Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor | Peichun Peter Liu, Christopher H. Olson | 2002-11-19 |
| 6480931 | Content addressable storage apparatus and register mapper architecture | Taqi Nasser Buti, Peter Juergen Klim, Hung Q. Le | 2002-11-12 |
| 6463524 | Superscalar processor and method for incrementally issuing store instructions | Maureen A. Delaney, Hung Q. Le, Dung Q. Nguyen, David Wayne Victor | 2002-10-08 |
| 6345356 | Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs | John Edward Derrick, Lee Evan Eisen, Hung Q. Le | 2002-02-05 |
| 6336183 | System and method for executing store instructions | Hung Q. Le, David Shippy, Larry Edward Thatcher | 2002-01-01 |
| 6256727 | Method and system for fetching noncontiguous instructions in a single clock cycle | — | 2001-07-03 |
| 6240507 | Mechanism for multiple register renaming and method therefor | John Edward Derrick, Soummy A Mallick | 2001-05-29 |
| 6212542 | Method and system for executing a program within a multiscalar processor by processing linked thread descriptors | James Allan Kahle, Soummya Mallick, Edward L. Swarthout | 2001-04-03 |
| 5961639 | Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution | Soummya Mallick, Edward L. Swarthout | 1999-10-05 |
| 5913925 | Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order | James Allan Kahle, Soummya Mallick | 1999-06-22 |
| 5897666 | Generation of unique address alias for memory disambiguation buffer to avoid false collisions | Soummya Mallick | 1999-04-27 |
| 5887166 | Method and system for constructing a program including a navigation instruction | Soummya Mallick, Edward L. Swarthout | 1999-03-23 |
| 5812812 | Method and system of implementing an early data dependency resolution mechanism in a high-performance data processing system utilizing out-of-order instruction issue | Muhammad Afsar, Romesh Mangho Jessani, Soummya Mallick, Mukesh Sharma | 1998-09-22 |
| 5802386 | Latency-based scheduling of instructions in a superscalar processor | James Allan Kahle, Soummya Mallick | 1998-09-01 |