| 8065685 |
Method, system and apparatus for a transformation engine for use in the processing of structured documents |
Daniel Martin Cermak, Howard P. Tsoi, Richard Trujillo, Udi Kalekin, Bryan Dobbs +3 more |
2011-11-22 |
| 6574727 |
Method and apparatus for instruction sampling for performance monitoring and debug |
Joel Roger Davidson, Alexander Erik Mericas |
2003-06-03 |
| 6442675 |
Compressed string and multiple generation engine |
Lee Evan Eisen, Hung Q. Le |
2002-08-27 |
| 6430678 |
Scoreboard mechanism for serialized string operations utilizing the XER |
James Allan Kahle, Hung Q. Le, Lee Evan Eisen, Robert William Hay |
2002-08-06 |
| 6425069 |
Optimization of instruction stream execution that includes a VLIW dispatch group |
Larry Edward Thatcher |
2002-07-23 |
| 6385719 |
Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor |
Brian R. Konigsburg, Lee Evan Eisen, David S. Levitan |
2002-05-07 |
| 6345356 |
Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs |
Lee Evan Eisen, Hung Q. Le, Robert G. McDonald |
2002-02-05 |
| 6336182 |
System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch |
Lee Evan Eisen, Paul J. Jordan, Robert William Hay |
2002-01-01 |
| 6321380 |
Method and apparatus for modifying instruction operations in a processor |
Lee Evan Eisen, Kevin F. Reick |
2001-11-20 |
| 6304959 |
Simplified method to generate BTAGs in a decode unit of a processing system |
Brian R. Konigsburg, David S. Levitan |
2001-10-16 |
| 6289428 |
Superscaler processor and method for efficiently recovering from misaligned data addresses |
Hung Q. Le, David Shippy, Larry Edward Thatcher |
2001-09-11 |
| 6286094 |
Method and system for optimizing the fetching of dispatch groups in a superscalar processor |
Lee Evan Eisen, Hung Q. Le, Brian R. Konigsburg |
2001-09-04 |
| 6240507 |
Mechanism for multiple register renaming and method therefor |
Soummy A Mallick, Robert G. McDonald |
2001-05-29 |
| 5983025 |
Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses |
William R. Greer, Christopher M. Herring |
1999-11-09 |
| 5906659 |
Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses |
William R. Greer, Christopher M. Herring |
1999-05-25 |
| 5890216 |
Apparatus and method for decreasing the access time to non-cacheable address space in a computer system |
Christopher M. Herring |
1999-03-30 |
| 5872980 |
Semaphore access control buffer and method for accelerated semaphore operations |
Christopher M. Herring |
1999-02-16 |
| 5787486 |
Bus protocol for locked cycle cache hit |
Henry Chin, Christopher M. Herring, George Totolos, Jr. |
1998-07-28 |
| 5704058 |
Cache bus snoop protocol for optimized multiprocessor computer system |
Christopher M. Herring |
1997-12-30 |
| 5659710 |
Cache coherency method and system employing serially encoded snoop responses |
Kevin Sherman |
1997-08-19 |
