Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7961654 | System and method for concurrent wireless voice and data communications | Dannie Gerrit Feekes | 2011-06-14 |
| 7177287 | System and method for concurrent wireless voice and data communications | Dannie Gerrit Feekes | 2007-02-13 |
| 6958987 | DECT-like system and method of transceiving information over the industrial-scientific-medical spectrum | Dannie Gerrit Feekes, Alexandre Jose C. Silva Sousa | 2005-10-25 |
| 6652404 | Device for assembling a push V-belt | — | 2003-11-25 |
| 6629157 | System and method for virtualizing the configuration space of PCI devices in a processing system | Brian Dennis Falardeau, David W. Nuechterlein, Jonathan White | 2003-09-30 |
| 5983025 | Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses | John Edward Derrick, William R. Greer | 1999-11-09 |
| 5906659 | Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses | John Edward Derrick, William R. Greer | 1999-05-25 |
| 5890216 | Apparatus and method for decreasing the access time to non-cacheable address space in a computer system | John Edward Derrick | 1999-03-30 |
| 5884094 | Computer system for detecting and accessing BIOS ROM on the local or peripheral bus | Ralph M. Begun, William R. Greer | 1999-03-16 |
| 5872980 | Semaphore access control buffer and method for accelerated semaphore operations | John Edward Derrick | 1999-02-16 |
| 5860081 | Interfacing an L2 cache to a single bus having alternative protocols | Forrest E. Norrod | 1999-01-12 |
| 5802393 | Computer system for detecting and accessing BIOS ROM on local bus peripheral bus or expansion bus | Ralph M. Begun, William R. Greer | 1998-09-01 |
| 5787486 | Bus protocol for locked cycle cache hit | Henry Chin, John Edward Derrick, George Totolos, Jr. | 1998-07-28 |
| 5704058 | Cache bus snoop protocol for optimized multiprocessor computer system | John Edward Derrick | 1997-12-30 |
| 5680556 | Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses | Ralph M. Begun, William R. Greer | 1997-10-21 |
| 5627993 | Methods and systems for merging data during cache checking and write-back cycles for memory reads and writes | Richard P. Abato, William R. Greer | 1997-05-06 |
| 5553265 | Methods and system for merging data during cache checking and write-back cycles for memory reads and writes | Richard P. Abato, William R. Greer | 1996-09-03 |
| 5488691 | Memory card, computer system and method of operation for differentiating the use of read-modify-write cycles in operating and initializaiton modes | Daniel P. Fuoco, Mark W. Kellogg, Jorge E. Lenta | 1996-01-30 |
| 5459842 | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory | Ralph M. Begun, Paul W. Browne, Marc R. Faucher, Gerald L. Frank | 1995-10-17 |
| 5452429 | Error correction code on add-on cards for writing portions of data words | Daniel P. Fuoco, Mark W. Kellogg, Jorge E. Lenta | 1995-09-19 |
| 5404543 | Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes | Marc R. Faucher, Mark W. Kellogg | 1995-04-04 |
| 5375084 | Selectable interface between memory controller and memory simms | Ralph M. Begun, Mark W. Kellogg | 1994-12-20 |