Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8819484 | Dynamically reconfiguring a primary processor identity within a multi-processor socket server | Michael DeCesaris, Randolph S. Kolvick, Steven L. Vanderlinden | 2014-08-26 |
| 8032745 | Authentication of I2C bus transactions | Justin P. Bandholz, Andrew S. Heinzmann, Fernando A. Lopez | 2011-10-04 |
| 8028069 | Structure for securing leased resources on a computer | Justin P. Bandholz, Andrew S. Heinzmann, Fernando A. Lopez | 2011-09-27 |
| 7984312 | System and method for interchangeably powering single or multiple motherboards | Raymond M. Clemo, Brian Gormley, Michael S. Miller | 2011-07-19 |
| 7948196 | Plurality of configurable independent compute nodes sharing a fan assembly | Raymond M. Clemo, Karl Klaus Dittus, Vinod Kamath, Michael S. Miller, Warren Everett Price +1 more | 2011-05-24 |
| 7707290 | Securing leased resources on a computer | Justin P. Bandholz, Andrew S. Heinzmann, Fernando A. Lopez | 2010-04-27 |
| 7487222 | System management architecture for multi-node computer system | Adam L. Soderlund | 2009-02-03 |
| 5884094 | Computer system for detecting and accessing BIOS ROM on the local or peripheral bus | William R. Greer, Christopher M. Herring | 1999-03-16 |
| 5878256 | Method and apparatus for providing updated firmware in a data processing system | Richard Bealkowski, Louis Bennie Capps, Jr. | 1999-03-02 |
| 5826075 | Automated programmable fireware store for a personal computer system | Richard Bealkowski | 1998-10-20 |
| 5802393 | Computer system for detecting and accessing BIOS ROM on local bus peripheral bus or expansion bus | William R. Greer, Christopher M. Herring | 1998-09-01 |
| 5680556 | Computer system and method of operation thereof wherein a BIOS ROM can be selectively locatable on diffeent buses | William R. Greer, Christopher M. Herring | 1997-10-21 |
| 5459842 | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory | Paul W. Browne, Marc R. Faucher, Gerald L. Frank, Christopher M. Herring | 1995-10-17 |
| 5450559 | Microcomputer system employing address offset mechanism to increase the supported cache memory capacity | Patrick M. Bland, Mark E. Dean | 1995-09-12 |
| 5381541 | Computer system having planar board with single interrupt controller and processor card with plural processors and interrupt director | Michael R. Turner | 1995-01-10 |
| 5375084 | Selectable interface between memory controller and memory simms | Christopher M. Herring, Mark W. Kellogg | 1994-12-20 |
| 5327545 | Data processing apparatus for selectively posting write cycles using the 82385 cache controller | Patrick M. Bland, Mark E. Dean | 1994-07-05 |
| 5307482 | Computer, non-maskable interrupt trace routine override | Richard Bealkowski, Michael R. Turner | 1994-04-26 |
| 5182809 | Dual bus microcomputer system with programmable control of lock function | Patrick M. Bland, Philip E. Milling | 1993-01-26 |
| 5175826 | Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 | Patrick M. Bland, Mark E. Dean | 1992-12-29 |
| 5170481 | Microprocessor hold and lock circuitry | Patrick M. Bland, Mark E. Dean | 1992-12-08 |
| 5146582 | Data processing system with means to convert burst operations into memory pipelined operations | — | 1992-09-08 |
| 5125084 | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller | Patrick M. Bland, Mark E. Dean | 1992-06-23 |
| 5109506 | Microcomputer system including a microprocessor reset circuit | — | 1992-04-28 |
| 5045998 | Method and apparatus for selectively posting write cycles using the 82385 cache controller | Patrick M. Bland, Mark E. Dean | 1991-09-03 |