Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6073212 | Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags | Belliappa Kuttanna, Krishna M. Thatipelli, Ricky C. Hetherington, Fong Pong | 2000-06-06 |
| 6065097 | Apparatus and method for sharing a unified memory bus between external cache memory and primary memory | Gary F. Feierbach, Yanhua Sun, Marcel Dignum, Saed Muhssin | 2000-05-16 |
| 5987570 | Performing overlapping burst memory accesses and interleaved memory accesses on cache misses | Kumar Venkatasubramaniam | 1999-11-16 |
| 5909697 | Reducing cache misses by snarfing writebacks in non-inclusive memory systems | Ricky C. Hetherington, Belliappa Kuttanna, Fong Pong, Krishna M. Thatipelli | 1999-06-01 |
| 5781721 | Method and apparatus for testing cache RAM residing on a microprocessor | Adam Malamy, Rajiv Patel | 1998-07-14 |
| 5708792 | Method and apparatus for a coherent copy-back buffer in a multipressor computer system | Adam Malamy | 1998-01-13 |
| 5675765 | Cache memory system with independently accessible subdivided cache tag arrays | Adam Malamy, Rajiv Patel | 1997-10-07 |
| 5497480 | Broadcast demap for deallocating memory pages in a multiprocessor system | Pradeep Sindhu, Jean-Marc Frailong, Sunil Nanda | 1996-03-05 |
| 5440707 | Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle | Adam Malamy, Rajiv Patel | 1995-08-08 |
| 5353425 | Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature | Adam Malamy, Rajiv Patel | 1994-10-04 |
| 5353426 | Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete | Rajiv Patel, Adam Malamy | 1994-10-04 |
| 5329627 | Method and apparatus for a translation lookaside buffer with built-in replacement scheme in a computer system | Sunil Nanda | 1994-07-12 |