RP

Rajiv Patel

JN Juniper Networks: 15 patents #167 of 2,602Top 7%
Oracle: 7 patents #1,763 of 14,854Top 15%
Overall (All Time): #196,426 of 4,157,543Top 5%
22
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
9813339 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2017-11-07
9647940 Processing packets by a network device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2017-05-09
9258228 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2016-02-09
8879395 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2014-11-04
8804739 Processing packets by a network device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2014-08-12
8503304 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2013-08-06
8238246 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2012-08-07
8189576 Systems and methods for processing packets with multiple engines Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2012-05-29
7986629 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2011-07-26
7688727 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2010-03-30
7664045 Sampling to a next hop Kaushik Ghosh, Dennis C. Ferguson, Scott Mackie 2010-02-16
7230912 Sampling to a next hop Kaushik Ghosh, Dennis C. Ferguson, Scott Mackie 2007-06-12
7215637 Systems and methods for processing packets Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2007-05-08
6798777 Filtering and route lookup in a switching device Dennis C. Ferguson, Gerald Cheung, Pradeep Sindhu 2004-09-28
5909440 High speed variable length best match look-up in a switching device Dennis C. Ferguson, Pradeep Sindhu 1999-06-01
5781721 Method and apparatus for testing cache RAM residing on a microprocessor Norman M. Hayes, Adam Malamy 1998-07-14
5675765 Cache memory system with independently accessible subdivided cache tag arrays Adam Malamy, Norman M. Hayes 1997-10-07
5537665 Multiple bank column redundancy intialization controller for cache RAM Adam Malamy 1996-07-16
5440707 Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle Norman M. Hayes, Adam Malamy 1995-08-08
5390190 Inter-domain latch for scan based design Sunil Nanda 1995-02-14
5353425 Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature Adam Malamy, Norman M. Hayes 1994-10-04
5353426 Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete Adam Malamy, Norman M. Hayes 1994-10-04