Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8013765 | Modular scaleable processing engine for accelerating variable length coding | — | 2011-09-06 |
| 6529207 | Identifying silhouette edges of objects to apply anti-aliasing | Edouard Landau, Adrian Sfarti, Mei-Chi Liu, Robert Laker, Paolo E. Sabella | 2003-03-04 |
| 6219070 | System and method for adjusting pixel parameters by subpixel positioning | Nick Baker, Adrian Sfarti, Paul Paternoster, Padma Parthasarathy | 2001-04-17 |
| 6144387 | Guard region and hither plane vertex modification for graphics rendering | Mei-Chi Liu, Adrian Sfarti, Nicholas R. Baker, John Cumming | 2000-11-07 |
| 6115050 | Object-based anti-aliasing | Edouard Landau, Adrian Sfarti, Mei-Chi Liu, Robert Laker, Paolo E. Sabella | 2000-09-05 |
| 6100898 | System and method of selecting level of detail in texture mapping | Nicholas R. Baker, Adrian Sfarti, Victor Tirva | 2000-08-08 |
| 6094201 | Polygon rendering method and system with dedicated setup engine | Nicholas R. Baker, Robert Laker, Padma Parthasarathy, Adrian Sfarti | 2000-07-25 |
| 5856829 | Inverse Z-buffer and video display system having list-based control mechanism for time-deferred instructing of 3D rendering engine that also responds to supervisory immediate commands | Donald Gray, Robert Laker, Adrian Sfarti | 1999-01-05 |
| 5798762 | Controlling a real-time rendering engine using a list-based control mechanism | Adrian Sfarti, Nicholas R. Baker, Robert Laker | 1998-08-25 |
| 5781721 | Method and apparatus for testing cache RAM residing on a microprocessor | Norman M. Hayes, Rajiv Patel | 1998-07-14 |
| 5708792 | Method and apparatus for a coherent copy-back buffer in a multipressor computer system | Norman M. Hayes | 1998-01-13 |
| 5675765 | Cache memory system with independently accessible subdivided cache tag arrays | Rajiv Patel, Norman M. Hayes | 1997-10-07 |
| 5570376 | Method and apparatus for identifying faults within a system | Ramachandra P. Kunda, Marc E. Levitt | 1996-10-29 |
| 5537665 | Multiple bank column redundancy intialization controller for cache RAM | Rajiv Patel | 1996-07-16 |
| 5440707 | Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle | Norman M. Hayes, Rajiv Patel | 1995-08-08 |
| 5353425 | Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature | Rajiv Patel, Norman M. Hayes | 1994-10-04 |
| 5353426 | Cache miss buffer adapted to satisfy read requests to portions of a cache fill in progress without waiting for the cache fill to complete | Rajiv Patel, Norman M. Hayes | 1994-10-04 |