| 8549339 |
Processor core communication in multi-core processor |
Andrew Wolfe |
2013-10-01 |
| 6081913 |
Method for ensuring mutual exclusivity of selected signals during application of test patterns |
Sridhar Narayanan |
2000-06-27 |
| 5900757 |
Clock stopping schemes for data buffer |
Sandeep Aggarwal, Srinivas Nori |
1999-05-04 |
| 5898702 |
Mutual exclusivity circuit for use in test pattern application scan architecture circuits |
Sridhar Narayanan |
1999-04-27 |
| 5892778 |
Boundary-scan circuit for use with linearized impedance control type output drivers |
Farideh Golshan |
1999-04-06 |
| 5872796 |
Method for interfacing boundary-scan circuitry with linearized impedance control type output drivers |
Farideh Golshan |
1999-02-16 |
| 5870408 |
Method and apparatus for on die testing |
Sandeep Aggarwal, David Bertucci |
1999-02-09 |
| 5864564 |
Control circuit for deterministic stopping of an integrated circuit internal clock |
Harsimran S. Grewal |
1999-01-26 |
| 5850150 |
Final stage clock buffer in a clock distribution network |
Sundari Mitra, Prasad Chalasani |
1998-12-15 |
| 5787012 |
Integrated circuit with identification signal writing circuitry distributed on multiple metal layers |
— |
1998-07-28 |
| 5774474 |
Pipelined scan enable for fast scan testing |
Sridhar Narayanan |
1998-06-30 |
| 5570376 |
Method and apparatus for identifying faults within a system |
Ramachandra P. Kunda, Adam Malamy |
1996-10-29 |
| 5528165 |
Logic signal validity verification apparatus |
Slobodan Simovich, Srinivas Nori, Ramachandra P. Kunda |
1996-06-18 |
| 5513186 |
Method and apparatus for interconnect testing without speed degradation |
— |
1996-04-30 |
| 5379303 |
Maximizing improvement to fault coverage of system logic of an integrated circuit with embedded memory arrays |
— |
1995-01-03 |
| 5341382 |
Method and apparatus for improving fault coverage of system logic of an integrated circuit with embedded memory arrays |
— |
1994-08-23 |
