PC

Prasad Chalasani

IN Invecas: 7 patents #2 of 22Top 10%
ME Mediamath: 4 patents #7 of 20Top 35%
SO Soctronics: 4 patents #2 of 2Top 100%
YH Yahoo Holdings: 3 patents #543 of 2,500Top 25%
VE Verizon: 1 patents #3,381 of 6,226Top 55%
OA Oath: 1 patents #403 of 1,117Top 40%
SY Synopsys: 1 patents #1,143 of 2,302Top 50%
Oracle: 1 patents #8,282 of 14,854Top 60%
Overall (All Time): #171,030 of 4,157,543Top 5%
24
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11556964 Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platform Ari Buchalter, Ezra Winston, Jaynth Thiagarajan 2023-01-17
11170413 Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platform Ari Buchalter, Ezra Winston, Jaynth Thiagarajan 2021-11-09
11144937 Framework for marketplace analysis Tarun Bhatia, Rohit Chandra 2021-10-12
10977697 Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platform Ari Buchalter, Ezra Winston, Jaynth Thiagarajan 2021-04-13
10791203 Multi-protocol receiver Venkata N. S. N. Rao, Majid Jalali Far 2020-09-29
10505550 Method and apparatus of operating synchronizing high-speed clock dividers to correct clock skew Shaolei Quan, Vijay Gadde 2019-12-10
10502769 Digital voltmeter William Loh, Venkata N. S. N. Rao 2019-12-10
10467659 Methods, systems, and devices for counterfactual-based incrementality measurement in digital ad-bidding platform Ari Buchalter, Ezra Winston, Jaynth Thiagarajan 2019-11-05
10361684 Duty cycle detection Venkata N. S. N. Rao, Majid Jalali Far, Aram Martirosyan 2019-07-23
10094859 Voltage detector Venkata N. S. N. Rao, Majid Jalali Far 2018-10-09
10037540 Framework for marketplace analysis Tarun Bhatia, Rohit Chandra 2018-07-31
10014866 Clock alignment scheme for data macros of DDR PHY Narasimhan Vasudevan, Venkata N. S. N. Rao 2018-07-03
9971975 Optimal data eye for improved Vref margin Venkata N. S. N. Rao, Ravindra Kantamani 2018-05-15
9954538 Clock alignment scheme for data macros of DDR PHY Narasimhan Vasudevan, Venkata N. S. N. Rao 2018-04-24
9948310 Methods and systems for clocking a physical layer interface Venkata N. S. N. Rao 2018-04-17
9715907 Optimal data eye for improved Vref margin Venkata N. S. N. Rao, Ravindra Kantamani 2017-07-25
9564905 Methods and systems for clocking a physical layer interface Venkata N. S. N. Rao 2017-02-07
9467149 Methods and systems for distributing clock and reset signals across an address macro Venkata N. S. N. Rao 2016-10-11
9349421 Memory interface Venkata N. S. N. Rao 2016-05-24
9183564 Framework for marketplace analysis Tarun Bhatia, Rohit Chandra 2015-11-10
9152920 System and method of event publication in a goal achievement platform Tarun Bhatia, Sam Fishman, Eric Bax 2015-10-06
8667133 Methods and systems for determining the effect of a host on network latency while delivering online ADS Ayman Farahat, Tarun Bhatia 2014-03-04
6864732 Flip-flop circuit with reduced power consumption 2005-03-08
5850150 Final stage clock buffer in a clock distribution network Sundari Mitra, Marc E. Levitt 1998-12-15